Data optimization: Allocation of arrays to reduce communication on SIMD machines

Knobe, Kathleen; Lukas, Joan D.; Stelle, Guy L.

doi:10.1016/0743-7315(90)90086-5

Cited by 179 publications

(58 citation statements)

References 3 publications

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“…This problem is related to the problem of choosing good data decompositions in languages such as High Performance Fortran [34]. We expect that the techniques for layout optimization developed in the vector and parallel computing context (e.g., [11,25,31,32,41]) can be adapted to the hierarchical memory situation. Table 2 describes benchmark suite that we use to evaluate nonlinear array layout functions.…”

Section: Discussionmentioning

confidence: 99%

Nonlinear array layouts for hierarchical memory systems

Chatterjee

Jain

Lebeck

et al. 1999

Proceedings of the 13th International Conference on Supercomputing

124

142

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Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory. This layout function is fixed at language definition time and constitutes an invisible, non-programmable array attribute. In reality, modern memory systems are architecturally hierarchical rather than flat, with substantial differences in performance among different levels of the hierarchy. This mismatch between the model and the true architecture of memory systems can result in low locality of reference and poor performance. Some of this loss in performance can be recovered by re-ordering computations using transformations such as loop tiling. We explore nonlinear array layout functions as an additional means of improving locality of reference. For a benchmark suite composed of dense matrix kernels, we show by timing and simulation that two specific layouts (4D and Morton) have low implementation costs (2-5% of total running time) and high performance benefits (reducing execution time by factors of 1.1-2.5); that they have smooth performance curves, both across a wide range of problem sizes and over representative cache architectures; and that recursion-based control structures may be needed to fully exploit their potential.

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Section: Discussionmentioning

confidence: 99%

Nonlinear array layouts for hierarchical memory systems

Chatterjee

Jain

Lebeck

et al. 1999

Proceedings of the 13th International Conference on Supercomputing

124

142

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“…a set of edgt's linking dimensions of array~ (in tfw lhs of a~sigmrwnt stat<>ments) ~uhscriptcd by its loop control variable art> added in tlw D"\C. :\"ote that these <'dges arc differ-PHI than the indqH·ndt>nC<' antiprcfcn·nce edgPs delined in [16]. Tlwy characterize potentially paralleli- :-.Jodcs in the same subset correspond to dimension' to be aligned.…”

Section: Including Parallelization Constraints In the Dagmentioning

confidence: 99%

“…Some of the proposals presented in the literature about array r~mapping [:'i. [13][14][15][16][17][18][19][20] art> ~umm:uized in the rest of this section.…”

Section: Introductionmentioning

confidence: 99%

DDT: A Research Tool for Automatic Data Distribution in High Performance Fortran

Ayguadé

García

Gironès

et al. 1997

Scientific Programming

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This article describes the main features and implementation of our automatic data distribution research tool. The tool (DDT) accepts programs written in Fortran 77 and generates High Performance Fortran (HPF) directives to map arrays onto the memories of the processors and parallelize loops, and executable statements to remap these arrays. DDT works by identifying a set of computational phases (procedures and loops). The algorithm builds a search space of candidate solutions for these phases which is explored looking for the combination that minimizes the overall cost; this cost includes data movement cost and computation cost. The movement cost reflects the cost of accessing remote data during the execution of a phase and the remapping costs that have to be paid in order to execute the phase with the selected mapping. The computation cost includes the cost of executing a phase in parallel according to the selected mapping and the owner computes rule. The tool supports interprocedural analysis and uses control flow information to identify how phases are sequenced during the execution of the application.

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“…These algorithms are quite general, but assume that the location and dimensions of each matrix is known compile-time. The related problem of determining optimal initial allocation of matrices is discussed in [14].…”

Section: Improvementmentioning

confidence: 99%