Abstract:The memory subsystem is the performance bottleneck for data intensive applications, which makes it a key consideration in high-performance embedded system optimization. Onchip SRAMs including scratchpad memories (SPMs) and caches are widely used in embedded systems to narrow the speed gap between CPU and memory. However, many existing SPM data allocation algorithms are designed for architectures with pure SPM as on-chip SRAM. As a result, for off-the-shelf embedded processors with hybrid on-chip scratchpad and… Show more
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