Dark silicon aware runtime mapping for many-core systems: A patterning approach

Kanduri, Anil; Haghbayan, Mohammad-Hashem; Rahmani, Amir-Mohammad; Liljeberg, Pasi; Jantsch, Axel; Tenhunen, Hannu

doi:10.1109/iccd.2015.7357167

Cited by 41 publications

(35 citation statements)

References 25 publications

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“…The many-core system floorplanning can be found in [37]. The temperature threshold is 60 o C. We compare our approach with the following two runtime thermal-aware mapping algorithms that aim to dark silicon era, (1) DsRem [24], where the cores on/off patterning are identified followed by tasks mapped to active cores, and (2) PAT [22], where a core region including inactive cores is found for each application. To augment existing algorithms, we assign a maximum of max {|A i |, Γ} bubbles to each application, where |A i | is the number of tasks of each application and Γ is the number of available bubble in the system.…”

Section: Methodsmentioning

confidence: 99%

“…However, these approaches do not consider a power budget for the whole chip, which is desired in the dark silicon era. There has been some efforts to perform the mapping by taking the power budget into account [19], [22], [28], [35]. Some of these efforts just try to respect the power budget, whereas others try for the thermal design power budget.…”

Section: Related Workmentioning

confidence: 99%

“…To address dark silicon problem while considering multiple applications, recently, some resource allocation approaches have been introduced [22], [24]. The approach in [24] identifies the number, location and voltage/frequency levels of active cores for each application to optimize the .…”

Section: Related Workmentioning

confidence: 99%

“…In such cases, the appropriate location of active cores not only help to optimize the peak temperature but also the communication time/performance. The approach in [22] leverages dark silicon to balance the temperature of active cores to provide higher power budget and better resource utilization, within a safe peak operating temperature. Dynamic workloads are considered and this approach aligns active cores along with dark cores that can evenly distribute heat dissipation across the chip.…”

Section: Related Workmentioning

confidence: 99%

“…For the other two approaches, DsRem [24] and PAT [22], their overhead or complexities are independent of the number of bubbles. However, the overhead of our proposed approach is comparable to that of PAT, and lower than that of DsRem.…”

Section: Complexity Analysismentioning

confidence: 99%

See 4 more Smart Citations

Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems

Wang

Singh

et al. 2016

2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)

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Abstract-All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores (referred to as bubbles) can be placed near active cores for heat dissipation so that the active cores can run at a higher frequency level, boosting the performance of applications that run on active cores. Budgeting inactive cores (bubbles) to applications to boost performance has the following three challenges. First, the number of bubbles varies due to open workloads. Second, communication distance increases when a bubble is inserted between two communicating tasks (a task is a thread or process of a parallel application), leading to performance degradation. Third, budgeting too many bubbles as coolers to running applications leads to insufficient cores for future applications. In order to address these challenges, in this paper, a bubble budgeting scheme is proposed to budget free cores to each application so as to optimize the throughput of the whole system. Throughput of the system depends on the execution time of each application and the waiting time incurred for newly arrived applications. Essentially, the proposed algorithm determines the number and locations of bubbles to optimize the performance and waiting time of each application, followed by tasks of each application being mapped to a core region. A Rollout algorithm is used to budget power to the cores as the last step. Experiments show that our approach achieves 50% higher throughput when compared to state-of-the-art thermal-aware runtime task mapping approaches. The runtime overhead of the proposed algorithm is in the order of 1M cycles, making it an efficient runtime task management method for large-scale many-core systems.

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Section: Methodsmentioning

confidence: 99%