DABC-NV: A buffer cache architecture for mobile systems with heterogeneous flash memories

Park, Junseok; Lee, Eunji; Bahn, Hyokyung

doi:10.1109/tce.2012.6414991

Cited by 12 publications

(6 citation statements)

References 16 publications

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“…Most works classify the data or write operations as hot or cold depending on length of write requests or random/sequential nature 8,10,15,18,24,34,35,38,41,45,47,51 or access frequency 8,45 to store them to different memory cells. 39,46 Also, data may be stored in SLC or MLC based on performance/deadline 9 and instantaneous wear 18 considerations. 15 Other works classify the data as user data or ECC data 32 and write or read intensive.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…15 Other works classify the data as user data or ECC data 32 and write or read intensive. 39,46 Also, data may be stored in SLC or MLC based on performance/deadline 9 and instantaneous wear 18 considerations.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…In case no SLC superblock is free, GC is performed and a victim is selected in the following order Park et al 46 note that since the data stored in volatile RAM (VRAM) buffer may be lost on a power failure or system crash, most systems use pdflush mechanism to periodically (eg, 30 seconds in Linux) write updated data to storage, even when the buffer has free space. This, however, contributes ∼80% of the writes to Flash memory and thus, increases the Flash writes significantly.…”

Section: Using Scms or Dram As A Buffermentioning

confidence: 99%

“…Otherwise, an LSBA is searched, which has SLC superblocks with more invalid pages than the total pages in one SLC superblock (3). Overall, their hierarchical update approach improves lifetime and write performance of SSD significantly.Park et al46 note that since the data stored in volatile RAM (VRAM) buffer may be lost on a power failure or system crash, most systems use pdflush mechanism to periodically (eg, 30 seconds in Linux) write updated data to storage, even when the buffer has free space. Hence, an SLC superblock (update area) is selected and merged with an MLC superblock (data area).…”

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A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

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Flash memory-based solid-state drives (SSDs) offer several attractive features and benefits compared to hard disk drive (HDD), such as shock resistance and better performance especially for random data access. Depending on the number of bits in each cell, Flash memory can be designed as single/multi/triple level cell (SLC/MLC/TLC), which have different performance, density, cost and write endurance characteristics. To bring the best of these together, several researchers have proposed designing SSD using hybrid SLC/MLC/TLC Flash memory. However, these SSDs also present several challenges such as buffer management, placement of hot/cold data in suitable portion, and intelligent garbage collection. Several recent techniques aim to address these challenges.In this paper, we present a survey of techniques for managing SSDs designed with SLC/MLC/TLC Flash memory. We classify the works on several axes to bring out their similarities and differences.We aim to synthesize the state-of-art progress in hybrid SSD management and also spark further research in this area. KEYWORDSflash translation layer, garbage collection, hybrid solid state disk, NAND flash memory, wear leveling INTRODUCTIONAs the amount of digital data continues to grow at an exponential rate and key applications become more data intensive, efficient storage architectures and management techniques have become more important than ever before. Conventionally, hard disk drive* has been used as a storage device; however, its limitations such as poor performance (especially for random accesses), higher form factor, and vulnerability to shocks and magnetic fields have encouraged researchers to explore its alternatives.Flash memory is a promising technology for designing storage devices due to its several attractive properties, eg, high performance and density, low power consumption, noise-free operation, and immunity to shocks and magnetic fields. 2-6 Also, its cost has been decreasing in recent years and it is expected to provide even better cost efficiency than HDD in near future. Based on the number of bits stored in each cell, Flash can be characterized as SLC (1 bit), MLC † (2 bit) and TLC (3 bits). As shown in Table 1, these cell types provide a spectrum of properties and trade-offs. Specifically, on going from SLC to MLC to TLC, the performance and write endurance decrease whereas density and cost efficiency improve.To achieve the best of these three cell types, hybrid SSD designs have been proposed, which use Flash memories of multiple cell types to improve performance, energy efficiency, and reliability. 16 However, these hybrid SSD designs also bring challenges, such as selection of relative proportion of SLC/MLC/TLC, efficient mapping/moving of hot/cold data to them, accounting for their disparate write endurance and density values, and

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Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Using Scms or Dram As A Buffermentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

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“…Buffer cache stores requested files read from storage in a certain part of memory area, which allows fast accesses of the same file data in subsequent requests [5][6][7][8]. As the size of the buffer cache is limited, we need to select an eviction victim in order to store new data.…”

Section: Introductionmentioning

confidence: 99%

File Type and Access Pattern Aware Buffer Cache Management for Rendering Systems

Shin¹,

Cho

Bahn³

2020

Electronics

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Rendering is the process of generating high-resolution images by software, which is widely used in animation, video games and visual effects in movies. Although rendering is a computation-intensive job, we observe that storage accesses may become another performance bottleneck in desktop-rendering systems. In this article, we present a new buffer cache management scheme specialized for rendering systems. Unlike general-purpose computing systems, rendering systems exhibit specific file access patterns, and we show that this results in significant performance degradation in the buffer cache system. To cope with this situation, we collect various file input/output (I/O) traces of rendering workloads and analyze their access patterns. The results of this analysis show that file I/Os in rendering processes consist of long loops for configuration, short loops for texture input, random reads for input, and single-writes for output. Based on this observation, we propose a new buffer cache management scheme for improving the storage performance of rendering systems. Experimental results show that the proposed scheme improves the storage I/O performance by an average of 19% and a maximum of 55% compared to the conventional buffer cache system.

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SSD internal cache management policies: A survey

Tripathy

Satpathy

2022

Journal of Systems Architecture

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DABC-NV: A buffer cache architecture for mobile systems with heterogeneous flash memories

Cited by 12 publications

References 16 publications

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

File Type and Access Pattern Aware Buffer Cache Management for Rendering Systems

SSD internal cache management policies: A survey

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