Cylindrical SOI Schottky Barrier MOSFET with High Linearity and Low Static Power for Digital and Analog Circuits Application

Abstract

Non-linearity and static power consumption are major challenges in the designing of digital and analog circuits. To improve the performance of digital and analog circuits, a proper selection of MOSFET device architecture is essential. The MOSFET device architecture with low static power dissipation and high linearity results in improves overall performance at the circuit level. In this work, a detailed analysis of cylindrical Silicon-on-Insulator (SOI) Schottky Barrier (SB) MOSFET is done for analog and digital circuit applications. The analog device parameters and device non-linearity parameters for SOI SB MOSFET are extracted and compared with SB MOSFET and Dielectric Pocket (DP) SB MOSFET. The SOI SB MOSFET shows an improvement of 6.905% in output conductance (gds), 130.513% in early voltage (Vea), 240.74% in transconductance generation factor (TGF), 35.901% in transconductance frequency product (TFP), 23.529% in the gain-bandwidth product (GBWP), 25.542% in voltage gain (Av), 130.968% in gain frequency product (GFP), and 179.964% in gain transconductance frequency product (GTFP). Third-order extrapolated voltage (VIP3), third-order extrapolated power (IIP3), and extrapolated intermodulation power (IMD3) have also improved in comparison to SB MOSFET. The Atlas 3-D device simulation tool is used for numerical simulations.