Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part II: Modeling

Resnati, Davide; Nicosia, Gianluca; Paolucci, Giovanni M.; Visconti, A.; Compagnoni, Christian Monzio

doi:10.1109/ted.2016.2617890

Cited by 13 publications

(18 citation statements)

References 25 publications

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“…The reduction in the nonuniformities in channel electrostatics with temperature arises both from the reduction in trap occupancy at the grain boundaries [12] and to a less severe constraint of thermionic emission. All of these points must be carefully considered when addressing the variety of phenomena affected by percolative channel conduction, such as RTN [7,13,19,[34][35][36] and charge detrapping [37][38][39][40], when performing spectroscopic analyses of oxide traps based on local tunneling currents [41][42][43][44] and when addressing the impact of localized electron storage in charge trap layers on nonuniform channel inversion [45].…”

Section: Current Variabilitymentioning

confidence: 99%

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

et al. 2020

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In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

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Section: Current Variabilitymentioning

confidence: 99%

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

et al. 2020

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“…The concept of distributed cycling conditions was then proposed in [221] as a way to better emulate the real array behavior by performing either a uniform cycling over a longer time or several groups of fast cycles preceded by bake times, usually at high temperature to accelerate the charge loss. However, the previous model shows its limitations when dealing with highly non-uniform cycling patterns, calling for a more comprehensive interpretation of the trapping/detrapping physics, that was pursued in [223][224][225]227,233]. Such a model was built upon a few phenomenological assumptions: a Poisson distribution for the number of trapped electrons n t and a uniform distribution over a log-time axis of their detrapping time constant τ d .…”

Section: Modelsmentioning

confidence: 99%

“…In particular, it was noted that charge detrapping is enhanced with the oxide electric field and that little or no detrapping takes place during bake phases performed with cells in the erased state [227,237], suggesting that holes may play a non-negligible role in what is usually described as an electron-only detrapping process [238]. These developments led to a recent refinement of the above-mentioned model [225,233] that goes beyond the classical vision of pure charge detrapping, considering multiple-state defects related to structural relaxation of the oxide network. A pictorial view of the proposed defect states can be seen in Figure 27, where the lower states D2 and N2 represent the usual trapping/detrapping phenomena, for which the model discussed so far still holds (besides a minor modification to account for trapping).…”

Section: Modelsmentioning

confidence: 99%

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…Most of them focus on the single memory cell [5]- [7], and the comprehensively analysis of different physical failure mechanisms [5], [6] and the influence of states of adjacent cells [7] are presented. Some works study on the effects of data retention times, operation temperatures, and P/E cycles on retention characteristics [8]- [11] of NAND flash memory, and the universal retention V th degradation formula is developed. Besides, several modeling approaches have been proposed to predict the retention V th distributions based on array statistical behavior, such as: assuming the retention V th distributions as a mixture of Gaussian [12], [13] and other distribution functions, or fitting the V th distributions by parameter estimation algorithms [14]- [16], or using the experimental results to interpolation or extrapolation [17], and these modeling approaches nicely represent the retention V th distributions.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Wang

Lun³

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention V th distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated V th distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the V th distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory. INDEX TERMS Retention V th distribution, retention noise, 3-D TLC NAND flash memory, reliability.

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Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part II: Modeling

Cited by 13 publications

References 25 publications

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

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