Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem

Mian, Riaz-ul-haque; Shintani, Michihiro; Inoue, Michiko

doi:10.1109/socc46988.2019.1570559752

Cited by 1 publication

(3 citation statements)

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“…The proposed methods are evaluated and compared with the existing software and hardware intensive solutions. The proposed methods are implemented on an RISC-V based integrated framework for the software-hardware co-design proposed in Reference [21] (The integrated framework is available at https://decimalarith.info. ).…”

Section: Resultsmentioning

confidence: 99%

“…Figure 10 shows an overview of the RISC-V-based evaluation environment proposed in Reference [21]. The framework uses RISC-V ecosystem with input samples as decimal arithmetic verification test cases.…”

Section: Experiments Setupmentioning

confidence: 99%

“…Based on the analysis of both the existing software and hardware solutions, four methods for decimal multiplication are proposed. Herein, using the RISC-V-based evaluation environment proposed in Reference [21], it is experimentally demonstrated that these approaches are capable of speeding up the total execution process by 1.43× to 2.37× compared with a standard software library. In addition, 7-97% less hardware area overhead is required compared with a hardware solution where a coefficient multiplication is fully implemented in hardware.…”

Section: Introductionmentioning

confidence: 99%

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Hardware–Software Co-Design for Decimal Multiplication

Mian¹,

Shintani²,

Inoue³

2021

Computers

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Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.

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Section: Resultsmentioning

confidence: 99%

Section: Experiments Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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