Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study

Reduced bit low power VLSI architectures for motion estimation

“…Fig. 11 shows an architecture of an adder tree for RB parallel PE [3,[5][6][7][8][9][10] whereas a full resolution parallel adder tree would consist of eight 8-bit adders in the first level, four 9-bit adders in the second level, two 10-bit adders in the third level, a 11-bit adder in the fourth level and a 16-bit accumulator.…”

“…All the above mentioned architectures are then connected to one at a time with the serial RISC processor (through one address and data bus, i.e., loosely coupled configurations) to investigate the reduction in the computational complexity and power consumption [3,[5][6][7][8][9][10]. The architectures with the serial RISC processor form a processor-coprocessor system.…”

“…The FSME is the most computational part of MPEG2 encoder, i.e., the dynamic instruction count (instruction count at run time [5][6][7][8][9][10]) of FSME is 60% -80% of the encoder's total dynamic instruction count [3,[5][6][7][8][9][10]. The real time computational complexity of the FSME algorithm on a reduced instruction set computer (RISC) processor for a common intermediate format (CIF) video sequence involves billions of 8-bit arithmetic calculations and memory accesses per second [3].…”

“…These fast subsampling algorithms have less computational complexity although their quality can deteriorate as well. When these algorithms run on the multiprocessor based system [5][6][7][8][9][10], their computational complexity reduces further. VLSI implementations of these fast ME algorithms can become complex due to irregular data flow.…”

“…In [21][22][23], we presented FSME algorithms based on low resolution pixels along with a novel correction recovery mechanism based on spatial and temporal correlations among the pixels that have the benefits of high speed, low power and low area for VLSI architectures while the quality is kept at the same level. In [7][8][9][10], we considered benefits of data level parallelism and multiprocessing in reducing the computational complexity of ME process and proposed optimized architectures with respect to area, speed and power.…”