Current single event effects and radiation damage results for candidate spacecraft electronics

O'Bryan, Martha V.; LaBel, Kenneth A.; Ladbury, Raymond L.; Poivey, C.; Howard, J.W.; Reed, Robert A.; Kniffin, S.D.; Büchner, S.; Bings, J.P.; Titus, J.L.; Clark, Stephen; Turflinger, T.L.; Seidleck, C.M.; Marshall, C.J.; Marshall, P.W.; Kim, H.S.; Hawkins, D.K.; Carts, M.A.; Forney, James D.; Jones, Morris; Sanders, Anthony B.; Irwin, T.; Cox, S.R.; Kahric, Z.; Palor, C.; Sciarini, J.A.

doi:10.1109/redw.2002.1045537

Cited by 35 publications

(4 citation statements)

References 10 publications

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Section: B Experimental Results: Mosfetssupporting

confidence: 92%

“…Table 1 outlines each device category with relevant fabrication technology used, the approximate number of transistors in the device, and the performance metric used when reporting radiation tolerance. The specific IRLML5103 and IRLML2803 MOSFET devices were selected for their existing radiation effects literature [22] which allowed validation of the test setup through TID lifetime comparisons.…”

Section: B Device Selectionmentioning

confidence: 99%

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Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Holliday

Heuser

Manchester

et al. 2022

IEEE Trans. Aerosp. Electron. Syst.

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The survivability of microelectronic devices in ionizing radiation environments drives spacecraft design, capability, mission scope, and cost. This work exploits the periodic nature of many space radiation environments to extend device lifetimes without additional shielding or modifications to the semiconductor architecture. We propose a technique for improving component lifetimes through reduced total-dose accumulation by modulating device bias during periods of intense irradiation. Simulation of this "dynamic biasing" technique applied to singletransistor devices in a typical low-Earth orbit results in an increase of component life from 114 days to 477 days (318% improvement) at the expense of 5% down time (95% duty cycle). The biasing technique is also experimentally demonstrated using gamma radiation to study three commercial devices spanning a range of integrated circuit complexity in 109 rad/min and 256 rad/min dose rate conditions. The demonstrated improvements in device lifetimes using the proposed dynamic biasing technique lays a foundation for more effective use of modern microelectronics for space applications. Analogous to the role real-time temperature monitoring plays in maximizing modern processor performance, the proposed dynamic biasing technique is a means of intelligently responding to the radiation environment and capable of becoming an integral tool in optimizing component lifetimes in space.

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Section: B Experimental Results: Mosfetssupporting

confidence: 92%

Section: B Device Selectionmentioning

confidence: 99%

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Holliday

Heuser

Manchester

et al. 2022

IEEE Trans. Aerosp. Electron. Syst.

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show abstract

“…6, it can be estimated that the IRLML2803 will no longer meet the specified V T H of 1.8 V ± 30% at an approximate total dose of 30 krad (biased) and 40 krad (unbiased). This is in strong agreement with TID performance reported by O'Bryan [22] of 35 krad for the IRLML2803. C. Experimental Results: Switching Regulators Figure 7 illustrates the output voltage performance of the TPS82740 switching regulator under constant 10 mA load as measured during irradiation at a rate of 256 rad/min.…”

Section: B Experimental Results: Mosfetssupporting

confidence: 92%

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Holliday¹,

Heuser²,

Manchester³

et al. 2021

Preprint

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The survivability of microelectronic devices in ionizing radiation environments drives spacecraft design, capability, mission scope, and cost. This work exploits the periodic nature of many space radiation environments to extend device lifetimes without additional shielding or modifications to the semiconductor architecture. We propose a technique for improving component lifetimes through reduced total-dose accumulation by modulating device bias during periods of intense irradiation. Simulation of this ``dynamic biasing" technique applied to single-transistor devices in a typical low-Earth orbit results in an increase of component life from 114 days to 477 days (318% improvement) at the expense of 5% down time (95% duty cycle). The biasing technique is also experimentally demonstrated using gamma radiation to study three commercial devices spanning a range of integrated circuit complexity in 109 rad/min and 256 rad/min dose rate conditions. The demonstrated improvements in device lifetimes using the proposed dynamic biasing technique lays a foundation for more effective use of modern microelectronics for space applications. Analogous to the role real-time temperature monitoring plays in maximizing modern processor performance, the proposed dynamic biasing technique is a means of intelligently responding to the radiation environment and capable of becoming an integral tool in optimizing component lifetimes in space.

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“…As stated in [3,4], drastic device shrinking, power supply reduction, and increasing operating speeds significantly reduce the noise margins and thus the reliability that very deep submicron (VDSM) ICs face from the various internal sources of noise. This process is now approaching a point where it will be unfeasible to produce ICs that are free from these effects.…”

Section: Introductionmentioning

confidence: 99%

Designing and testing fault-tolerant techniques for SRAM-based FPGAs

Kastensmidt

Neuberger

Carro

et al. 2004

Proceedings of the 1st Conference on Computing Frontiers

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This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation.

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Current single event effects and radiation damage results for candidate spacecraft electronics

Cited by 35 publications

References 10 publications

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

Designing and testing fault-tolerant techniques for SRAM-based FPGAs

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