Current radiation issues for programmable elements and devices

Katz, Robert; Wang, J.J.; Koga, R.; LaBel, Kenneth A.; McCollum, J.; Brown, R. D.; Reed, Robert A.; Cronquist, B.; Crain, S.; Scott, Thomas R.; Paolini, W.; Sin, Benny

doi:10.1109/23.736503

Cited by 25 publications

(10 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Heavy-ion and pulsed-laser test data on RH1020, A1020B, A1020A and A1020 indicated that the most sensitive area is in the clock buffer [2]. The -junction of node X, shown in Fig.…”

Section: Heavy-ion Test and Spice Simulation Resultsmentioning

confidence: 99%

“…The data is measured on a shift register running at 1 MHz. The testing details can be found in a previous publication [2].…”

Section: Heavy-ion Test and Spice Simulation Resultsmentioning

confidence: 99%

“…3. Heavy-ion test results of clock upset for the pre-production (original clock) and production (redesigned clock) RH1020 device [2].…”

Section: Clock Buffer Circuitmentioning

confidence: 99%

“…If the SET-induced glitch is strong enough to be recognized by the circuit as a clock signal, the data stored in the flip-flop will be clocked out with incorrect timing. "Clock upset" was coined as the abbreviation for clock-SET-induced soft error in our previous publication [2] and will be used likewise in the remaining of this paper. For programmable logic devices such as a field programmable gate array (FPGA), a global clock circuit across the whole or partial chip is usually already designed-in (instead of programmed-in) for performance and ease of use.…”

Section: Introductionmentioning

confidence: 99%

“…It is also easy to configure for single event effect experiments. Manuscript During the development of a total-dose-hardened device, RH1020, one of Actel 1020 product family [3], clock upset was detected during heavy-ion tests at Brookhaven National Laboratory (BNL) [2]. The test data showed that the RH1020 was more sensitive than its commercial sibling, the A1020B, which has the same feature size.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Wang¹,

Katz

Dhaoui³

et al. 2000

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET . The difference between LET at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.

show abstract

“…Heavy-ion and pulsed-laser test data on RH1020, A1020B, A1020A and A1020 indicated that the most sensitive area is in the clock buffer [2]. The -junction of node X, shown in Fig.…”

Section: Heavy-ion Test and Spice Simulation Resultsmentioning

confidence: 99%

“…The data is measured on a shift register running at 1 MHz. The testing details can be found in a previous publication [2].…”

Section: Heavy-ion Test and Spice Simulation Resultsmentioning

confidence: 99%

“…3. Heavy-ion test results of clock upset for the pre-production (original clock) and production (redesigned clock) RH1020 device [2].…”

Section: Clock Buffer Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Wang¹,

Katz

Dhaoui³

et al. 2000

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

A design based on proven concepts of an SEU-immune CMOS configuration data cell for reprogrammable FPGAs

Rockett

2001

Microelectronics Journal

View full text Add to dashboard Cite

Si/a-Si Core/Shell Nanowires as Nonvolatile Crossbar Switches

et al. 2008

View full text Add to dashboard Cite

Radial core/shell nanowires (NWs) represent an important class of nanoscale building blocks with substantial potential for exploring fundamental electronic properties and realizing novel device applications at the nanoscale. Here, we report the synthesis of crystalline silicon/amorphous silicon (Si/a-Si) core/shell NWs and studies of crossed Si/a-Si NW metal NW (Si/a-Si x M) devices and arrays. Room-temperature electrical measurements on single Si/a-Si x Ag NW devices exhibit bistable switching between high (off) and low (on) resistance states with well-defined switching threshold voltages, on/off ratios greater than 10(4), and current rectification in the on state. Temperature-dependent switching experiments suggest that rectification can be attributed to barriers to electric field-driven metal diffusion. Systematic studies of Si/a-Si x Ag NW devices show that (i) the bit size can be at least as small as 20 nm x 20 nm, (ii) the writing time is <100 ns, (iii) the retention time is >2 weeks, and (iv) devices can be switched >10(4) times without degradation in performance. In addition, studies of dense one-dimensional and two-dimensional Si/a-Si x Ag NW devices arrays fabricated on crystalline and plastic substrates show that elements within the arrays can be independently switched and read, and moreover that bends with radii of curvature as small as 0.3 cm cause little change in device characteristics. The Si/a-Si x Ag NW devices represent a highly scalable and promising nanodevice element for assembly and fabrication of dense nonvolatile memory and programmable nanoprocessors.

show abstract

Current radiation issues for programmable elements and devices

Cited by 25 publications

References 7 publications

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

A design based on proven concepts of an SEU-immune CMOS configuration data cell for reprogrammable FPGAs

Si/a-Si Core/Shell Nanowires as Nonvolatile Crossbar Switches

Contact Info

Product

Resources

About