Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications

Abstract

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 m CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88 V, the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system.

Noise‐power‐area optimised design procedure for OTAs with complementary input transistors for neural amplifiers

“…Table 1 Comparison of the state-of-the-art neural amplifiers TBCAS, 2012 [16] Electro. Letters, 2012 [8] BioCAS, 2013 [14] TBCAS, 2013 [5] JSSC, 2013 [17] JSSC, 2017 [13] TBCAS, 2018 [18] TBCAS, 2018 [19] This work…”

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

“…The implementation is optimized for noise, thus a larger gain of 40 dB was used as compared to 26 dB [15]. As matching of the capacitors is crucial in this architecture to avoid CMRR degradation [23], the smallest capacitors C fb in the design were chosen to be 40 fF, which improves robustness to mismatch, but also requires a large C in = 4 pF for the targeted signal amplification, thereby adversely affecting R * in from Eq. (1).…”

“…(1). This highlights a trade-off between CMRR, which benefits from improved matching [23] in non-minimum sized capacitors, and the input impedance R in,boost , which depends more than proportionally on the input capacitor, as both R * in and the settling error x in Eq. (4) improve for decreasing C in .…”

Self-Biased Ultralow Power Current-Reused Neural Amplifier With On-Chip Analog Spike Detections

“…The current-reuse technique is suitable for achieving good noise performance with limited power consumption. Low power current-reuse neural amplifiers with high current and power efficiency have been reported [20]- [24], [27]- [29], [31]- [36]. In the current-reuse scheme, the input stage includes the complementary input stage of the PMOS differential input pair and the NMOS differential input pair.…”