Current and Future Challenges in Radiation Effects on CMOS Electronics

Dodd, P.E.; Shaneyfelt, M.R.; Schwank, J.R.; Felix, J.A.

doi:10.1109/tns.2010.2042613

Cited by 317 publications

(128 citation statements)

References 118 publications

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“…Ionizing radiation can also damage electronic circuits. "Radiation hardened" CMOS circuits have ratings of 1 -3 kGy [20]. So electronics would not survive long either.…”

Section: H Particle Flux and Energymentioning

confidence: 99%

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Speed kills: Highly relativistic spaceflight would be fatal for passengers and instruments

Edelstein

Edelstein²

2012

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Highly relativistic speeds are desirable for interstellar travel. Relativistic time dilation would reduce the subjective duration of the trip for the travelers, so that they can cover galaxy-scale distances in a reasonable amount of personal time. Unfortunately, as spaceship velocities approach the speed of light, interstellar hydrogen H, although only present at a density of approximately 1.8 atoms/cm 3 , turns into intense radiation that would quickly kill passengers and destroy electronic instrumentation. In addition, the energy loss of ionizing radiation passing through the ship's hull represents an increasing heat load that necessitates large expenditures of energy to cool the ship. Stopping or diverting this flux, either with material or electromagnetic shields, is a daunting problem. Going slow to avoid severe H irradiation sets an upper speed limit of v ~ 0.5 c. This velocity only gives a time dilation factor of about 15%, which would not substantially assist galaxy-scale voyages. Diffuse interstellar H atoms are the ultimate cosmic space mines and represent a formidable obstacle to interstellar travel.

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“…Ionizing radiation can also damage electronic circuits. "Radiation hardened" CMOS circuits have ratings of 1 -3 kGy [20]. So electronics would not survive long either.…”

Section: H Particle Flux and Energymentioning

confidence: 99%

“…We note that the annual dose limit for a radiation worker is 0.05 Sv (NRC, 2011), so shielding must be extremely effective to keep dose down to this level. Instrumentation must be similarly very well shielded, since even small doses over long times can exceed the cumulative dose limits for electronics of 1 -3 kGy [20,24].…”

mentioning

confidence: 99%

Speed kills: Highly relativistic spaceflight would be fatal for passengers and instruments

Edelstein

Edelstein²

2012

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“…This trend causes the circuits to be more sensitive to any disturbance such as noise, crosstalk, or ionizing particles, and they thus present an increased susceptibility to soft errors [4]. With this trend, the charge required to generate a SET at a node decreases while the operating frequency of the circuits increases.…”

Section: Introductionmentioning

confidence: 99%

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Calomarde

Amat

Moll

et al. 2014

Microelectronics Reliability

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Abstract-In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. This technology's independent design style achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. We propose two alternatives for this methodology in 7nm FinFET, and, to check the accuracy of our proposal, we compare them with previous techniques for hardening radiation at the transistor level against a Single Event Transient. Simulation results show that the proposed method has a higher soft error tolerance capability than existing methods as well as better noisy immunity.

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“…Additionally, transient errors due to cosmic neutrons, alpha particles, and radiation have emerged as key reliability concerns [2,3]. Error correction code (ECC) techniques have been used to enhance memory reliability.…”

Section: Introductionmentioning

confidence: 99%

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

Cha¹,

Yoon²

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.Index Terms-Error correction code, single error correction and double error detection code, check bit pre-computation, extended Hamming code and memory

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Current and Future Challenges in Radiation Effects on CMOS Electronics

Cited by 317 publications

References 118 publications

Speed kills: Highly relativistic spaceflight would be fatal for passengers and instruments

Speed kills: Highly relativistic spaceflight would be fatal for passengers and instruments

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Efficient Implementation of Single Error Correction and Double Error Detection Code with Check Bit Pre-computation for Memories

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