Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

Chen, Fen; Bravo, O. Martínez; Harmon, D.; Shinosky, M.; Aitken, J.

doi:10.1016/j.microrel.2008.06.037

Cited by 47 publications

(30 citation statements)

References 8 publications

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“…[108][109][110][111][112][113][114] Unfortunately, low-k ILD materials exhibit significantly reduced TDDB lifetimes relative to SiO 2 , and this is a significant, well documented concern for low-k/Cu interconnect reliability. [115][116][117][118] As will discussed later, low-k DB materials have also been observed to exhibit reduced TDDB lifetimes relative to a-Si 3 N 4 and a-SiN:H.…”

Section: Low-k Ild Cu Cumentioning

confidence: 89%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

127

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: Low-k Ild Cu Cumentioning

confidence: 89%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

127

115

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“…The dielectric breakdown time is defined as the time when the leakage current suddenly increases. Measurements were made on 12 samples under each condition and the Weibull distribution was used to express the dielectric breakdown times [17]. Two important parameters are used in the Weibull distribution analysis to evaluate the reliability of a dielectric film: T 63.2% is the characteristic breakdown time at which 63.2% failure has occurred and ˇ is the Weibull slope or shape parameter, which governs the distribution of the breakdown times.…”

Section: Resultsmentioning

confidence: 99%

Atomic layer deposition HfO2 capping layer effect on porous low dielectric constant materials

Cheng

Kao

Huang

et al. 2015

Applied Surface Science

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“…We note that models that describe backend TDDB, although they may have been initially developed for device TDDB, are of the general form [10]- [13] …”

Section: A Tddb Modelsmentioning

confidence: 99%

Backend dielectric chip reliability simulator for complex interconnect geometries

Chen

Bashir

Milor

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown.Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.

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Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

Cited by 47 publications

References 8 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Atomic layer deposition HfO2 capping layer effect on porous low dielectric constant materials

Backend dielectric chip reliability simulator for complex interconnect geometries

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