Backend dielectric chip reliability simulator for complex interconnect geometries

Abstract

Abstract-Backend dielectric breakdown degrades the reliability of circuits. We present test data and a methodology to estimate chip lifetime due to backend dielectric breakdown.Our methodology incorporates failures due to parallel tracks, the width effect, and field enhancement due to line ends. The impact of line ends has been found to be very significant experimentally, and it is demonstrated that this component can dominate the failure rate of the chip due to dielectric breakdown.

Backend dielectric reliability simulator for microprocessor system

“…The data collected from the test structures is presented in [13,17]. We've extracted g t and b t by fitting the data with a Weibull distribution.…”

“…The details of the test struc- tures, their design and results, are given in [13, 15,17]. The test structure in Fig.…”

“…In previous work, we have shown that full chip lifetimes may be affected by irregular geometries [17]. We also take into account the impacts of those irregular geometries in this work.…”

“…A given layout is analyzed by determining the pairs (S i , L i ) for each layer for all linespaces. The details of our methodology can be found in [13, [15][16][17].…”

“…The program then outputs a table for vulnerable areas and vulnerable features (#TLa/b, #TTa, #TTb, #PTT). The detailed explanation of Algorithm 1 is given in [17].…”