Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO<sub>2</sub>/Si Substrate for Via-last TSV Application

Matsudaira, Taro; Shindo, S.; Shimizu, Tomohiro; Ito, Tetsuo; Shinguhara, Shoso; Shimizu, Satoru

doi:10.1109/3dic48104.2019.9058791

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“…An electroless metal (EL) plating process is widely used to form conformal and seed layers. Matsudaira et al [40] have reported on Co-alloy as a barrier layer. On Pb nanoparticle catalyst, they have electroless plated CoWB and CoB.…”

Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

View full text Add to dashboard Cite

show abstract

Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO₂/Si Substrate for Via-last TSV Application

Cited by 1 publication

References 1 publication

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

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Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO2/Si Substrate for Via-last TSV Application

Cited by 1 publication

References 1 publication

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Contact Info

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Cu Diffusion Barrier Properties of Various CoWB Electroless Plated Films on SiO₂/Si Substrate for Via-last TSV Application