Cryogenic Characterization and Analysis of Nanoscale SOI FETs Using a Virtual Source Model

Zhou, Guantong; Mamun, Fahad Al; Yang-Scharlotta, Jean; Vasileska, Dragica; Esqueda, Ivan Sanchez

doi:10.1109/ted.2022.3142650

Cited by 13 publications

(4 citation statements)

References 33 publications

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“…As presented in figures 3(a) and (b), devices show a reduced V th when the temperature is raised. More accurately, device V th decreases linearly with a small plateau at cryogenic temperatures below 100 K (see figure S1), consistent with previous simulation and characterization results on n-type FDSOI MOSFETs [21][22][23]. For another, we extract device subthreshold swing (SS) values at 100 pA and list them in table 1.…”

Section: Resultssupporting

confidence: 85%

Electron transport characteristics in dual gate-controlled 30 nm-thick silicon membrane

Zhao¹,

Yuan²,

Zhang³

et al. 2022

J. Phys. D: Appl. Phys.

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The exploration of multi-gate-controlled electron transport characteristics is always a research focus in Si-based device development and optimization. In this work, we report individual and dual gate-controlled energy band regulations of 30 nm-thick Si membrane and the resulted electron transportations at 10 to 300 K. It is discovered that the fine energy band structure is a key element to determine electron transport behaviors in FDSOI. Furthermore, either the front or the back gate bias can modify the energy band bending and sub-band gap, change charged body distribution and intersub-band transition probability, and thus adjust electron mobility and device performance. This dual gate coupling effect together with the proposed gate-controlled sub-band structure model is confirmed by magnetotransport experiments at 1.6 K. Notably, our work presents the coupled gate controlling effects within ultrathin Si film, and gives a physical insight into electron structure modulating, which may promote the evolution of Si-based device applications in many domains.

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Section: Resultssupporting

confidence: 85%

Electron transport characteristics in dual gate-controlled 30 nm-thick silicon membrane

Zhao¹,

Yuan²,

Zhang³

et al. 2022

J. Phys. D: Appl. Phys.

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“…The drain current Id stabilizes at a temperature of 300 Kelvin. However, even though the drain current is low at low temperatures, it still represents an improvement over [45].…”

Section: 2comparative Studymentioning

confidence: 99%

“…The device was then subjected to temperature variation testing. As per reference [45], thermal effects cause changes in the channel temperature of FDSOI MOSFETs, which is due to the thickness and composition of the buried oxide, as well as the device's channel. At low temperatures, the device exhibits nonlinearity.…”

Section: 2comparative Studymentioning

confidence: 99%

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

2023

IJATEE

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The conventional silicon channel metal oxide semiconductor field effect transistor (MOSFET) has fundamental limits that are reached due to scalability, resulting in short-channel effects (SCE) and other issues in small-channel devices. To overcome these challenges and design a nanoscale device, an alternate material was needed. Graphene, a novel material with exceptional properties, has been utilized to create a graphene field-effect transistor (GFET) optimized using siliconon-insulator (SOI) technology. The SOI structure uses graphene as a channel, resulting in the development of a new silicon-on-insulator graphene field effect transistor (SIGFET) with an 18 nm channel length. The designed SIGFET exhibits significant improvements compared to traditional GFET and MOSFET. Specifically, the subthreshold slope (SS) of the SIGFET is 60.93 mV/decade, the drain-induced barrier lowering (DIBL) is 42.89 mV/V, and the ION/IOFF ratio is 6.55×108, which surpasses previous GFET-based contributions and SOI-MOSFET. Moreover, the effect of temperature change on SIGFET performance has been investigated, revealing that temperature variation only affects the drain current and has no impact on short channel characteristics. Therefore, the SIGFET can be an ideal substitute for traditional silicon channel devices.

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“…[10] (3) 自 2020 年开始, 美国官方先进智能研究机构 [12] . 美国麻省理工学院 (Massachusetts Institute of Technology) [13] 、圣母大学 (University of Notre Dame) [14] 和浙江大学 [10] 均利用虚拟源 (virtual source, VS) 模型对超薄沟道器件开展提参工作, 结果均显示, 100∼150 K 是迁移率和温度依存性关系变化的转折点. 由于低温逻辑芯片技术的工作环境是液氮, 因此, 在这一环境温度条件下, 载流子迁移率相较于室温是增加的, 可以利用这一特性改善器件工作速度, 这对高性能电路十分重要.…”

Section: 低温芯片技术和应用unclassified

Low-temperature CMOS technology for high-performance computing: development and challenges

CHENG,

LI,

WANG

et al. 2024

Sci. Sin.-Inf.

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等)、非超导存储器 (包括易失的静态随机存储器 (static random access memory, SRAM) [7] 、动态随机存储器 (dynamic random access memory, DRAM) [8] 、非易失的阻变存储器 (resistive random access memory, RRAM) [9] 、铁电存储器 (ferroelectric random access memory, FeRAM)、磁存储器 (magnetic random access memory, MRAM)、相变存储器 (phase-change random access memory, PCRAM) 等) 以

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Cryogenic Characterization and Analysis of Nanoscale SOI FETs Using a Virtual Source Model

Cited by 13 publications

References 33 publications

Electron transport characteristics in dual gate-controlled 30 nm-thick silicon membrane

Electron transport characteristics in dual gate-controlled 30 nm-thick silicon membrane

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

Low-temperature CMOS technology for high-performance computing: development and challenges

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