Cryogenic-Aware Forward Body Biasing in Bulk CMOS

Overwater, Ramon W. J.; Babaie, Masoud; Sebastiano, Fabio

doi:10.1109/led.2023.3337441

Cited by 4 publications

(1 citation statement)

References 19 publications

(21 reference statements)

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“…For both highprecision and high-speed applications, circuit techniques such as bootstrapping [55] should be used to circumvent this problem. Another technique that can be effectively used to deal with the increase in V th is the forward body biasing (FBB) [56]. By taking advantage of the increased turn-on voltage of parasitic diodes at cryogenic temperature, it is indeed possible to use the body terminal as a back-gate, similar to FDSOI technologies, without incurring large increases in leakage currents to the substrate.…”

Section: B Linear Regionmentioning

confidence: 99%

Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology

Gatti,

Tavernier

2024

IEEE J. Electron Devices Soc.

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This paper presents the cryogenic characterization and compact modeling of thin-oxide MOSFETs in a standard 65-nm Si-bulk CMOS technology. The influence of both short and narrow channel effects at extremely low temperature on key device parameters such as threshold voltage and ON current is highlighted, and the performance of this technology node for cryogenic analog circuit design is discussed. It is then demonstrated, for the widest range of gate geometries in literature, that the BSIM4 parameter editing approach can be successfully used to model small dimension effects at cryogenic temperature. In the absence of cryogenic foundry models, the robustness and simplicity of this modeling technique make it a preferred method to quickly build a design-oriented, fully scalable SPICE compact model. This restores complete freedom in device sizing for cryogenic analog circuit design.

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Section: B Linear Regionmentioning

confidence: 99%

Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology

Gatti,

Tavernier

2024

IEEE J. Electron Devices Soc.

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A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

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