Crosstalk-minimum layer assignment

Cho, J.D.; Raje, Salil; Sarrafzadeh, Majid; Sriram, M.; Kang, Sa-Ouk

doi:10.1109/cicc.1993.590822

Cited by 25 publications

(17 citation statements)

References 11 publications

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“…Their approach applies net ordering to the most timing-critical channel, followed by a space relaxation algorithm to reduce the coupling capacitance of the most timing-critical segment. Crosstalk reduction during layer assignment is addressed in Cho et al [1993]. Ho et al [2005] developed a crosstalk-driven TA in a multilevel routing system, decreasing crosstalk by identifying a minimum-cost (IRoute overlap length) Hamiltonian path of the currently processed clique obtained from the IRoute OLG.…”

Section: Crosstalk Optimization In Routingmentioning

confidence: 99%

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment

Chang

Cheng

2011

ACM Trans. Des. Autom. Electron. Syst.

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Track assignment, which is an intermediate stage between global routing and detailed routing, provides a good platform for promoting performance, and for imposing additional constraints during routing, such as crosstalk. Gridless track assignment (GTA) has not been addressed in public literature. This work develops a gridless routing system integrating a congestion-driven global router, crosstalk-driven GTA and an enhanced implicit connection-graph-based router. Initial assignment is produced rapidly with a left-edge like algorithm. Crosstalk reduction on the assignment is then transformed to a restricted nonslicing floorplanning problem, and a deterministic O-Tree based algorithm is employed to reassign each net segment. Finally, each panel is partitioned into several subpanels, and the subpanels are reordered using branch and bound algorithm to decrease the crosstalk further. Before detailed routing, routing tree construction is undertaken for placed IRoutes and other pins; many original point-to-point routings are set to connect to IRoutes, and can be accomplished simply with pattern routing. For detailed routing, this work proposes a rapid extraction method for pseudomaximum stripped tiles to boost path propagation. Experimental results demonstrate that the proposed gridless routing system has over 2.02 times the runtime speedup in average for fixed-and variablerule routings of an implicit connection-graph-based router, NEMO. As compared with a commercial routing tool, this work yields an average reduction rate of 13.8% in coupling capacitance calculated using its built-in coupling capacitance estimator.

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Section: Crosstalk Optimization In Routingmentioning

confidence: 99%

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment

Chang

Cheng

2011

ACM Trans. Des. Autom. Electron. Syst.

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“…We also determine the location of pins from soft blocks. We use an existing max-cut partitioning heuristic [35] for the net distribution in step 1. For step 2, we use an existing RSA/G heuristic [31] to generate the net topologies.…”

Section: A Overview Of the Approachmentioning

confidence: 99%

Placement and Routing for 3-D System-On-Package Designs

Minz

Wong

Pathak

et al. 2006

IEEE Trans. Comp. Packag. Technol.

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Abstract-Three-dimensional (3-D) packaging via system-onpackage (SOP) is a viable alternative to system-on-chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this article, we present the first physical design algorithms for thermal and power supply noise-aware 3-D placement and crosstalk-aware 3-D global routing. Existing approaches consider the thermal distribution, power supply noise, and crosstalk issues as an afterthought, which may require an expensive cooling scheme, more decoupling capacitors (=decap), and additional routing layers. Our goal is to overcome this problem with our thermal/decap/crosstalk-aware 3-D layout automation tools. The traditional design objectives such as performance, area, wirelength, and via are considered simultaneously to ensure high quality results. The related experimental results demonstrate the effectiveness of our approaches.Index Terms-Crosstalk, mixed-signal CAD, placement and routing, power supply noise, system-on-package (SOP), thermal distribution, three-dimensional (3-D) packaging.

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“…In the case where a horizontal segment is on more than one layer, as the outcome of a layer assignment algorithm [29], the problem can be approached in two different ways. The intraplane vias can be treated as additional variables where the location of these vias also needs to be determined.…”

Section: Two-terminal Net With Multiple Viasmentioning

confidence: 99%

Timing-driven via placement heuristics for three-dimensional ICs

Pavlidis

Friedman

2008

Integration

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The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion. r

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Crosstalk-minimum layer assignment

Cited by 25 publications

References 11 publications

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment

Placement and Routing for 3-D System-On-Package Designs

Timing-driven via placement heuristics for three-dimensional ICs

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