Cross-correlation of specification and RTL for soft IP analysis

Singh, Bhanu Pratap; Shankar, Arunprasath; Wolff, Francis; Papachristou, C.; Weyer, Daniel; Clay, Steve

doi:10.7873/date.2014.303

Cited by 6 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The second scheme is to obtain the trusted IP as much as possible. The third method relies on a new paradigm of expert-system-based IP analysis [120,121].…”

Section: Ip Verificationmentioning

confidence: 99%

Hardware Trojans in Chips: A Survey for Detection and Prevention

Dong

Liu

et al. 2020

Sensors

View full text Add to dashboard Cite

Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

show abstract

“…The second scheme is to obtain the trusted IP as much as possible. The third method relies on a new paradigm of expert-system-based IP analysis [120,121].…”

Section: Ip Verificationmentioning

confidence: 99%

Hardware Trojans in Chips: A Survey for Detection and Prevention

Dong

Liu

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…For example, "floating-point add" is a concept with"precision" and "single/double" as its associated feature and attributes respectively. For our prior work on spec analysis [7] and spec vs. RTL cross-correlation [8], ontologies were manually created by our experts which was rather a time-consuming process. Thus, there is a necessity to automate this process which would pave way for faster knowledge extraction and acquisition.…”

Section: Introductionmentioning

confidence: 99%

Ontology-guided Conceptual Analysis of Design Specifications

Shankar

Singh

Wolff

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

Self Cite

View full text Add to dashboard Cite

The integration of reusable IP blocks/cores is a common process in system-on-chip design and involves manually comparing/mapping IP specifications against system requirements. The informal nature of specification limits its automatic analysis. Existing techniques fail to utilize the underlying conceptual information embedded in specifications. In this paper, we present a methodology for specification analysis, which involves concept mining of specifications to generate domain ontologies. We employ a semi-supervised expert system with semantic analysis capability to create a collaborative framework for cumulative knowledge acquisition. Our system then uses the generated ontologies to perform component retrieval, drop-in-replacement analysis and design vs. test-plan comparisons. We demonstrate our approach by evaluating several IP specifications.

show abstract

“…Using formal check is discussed in [1,3], the advantage of formal check is obvious compared to conventional simulation techniques. The characteristics of RTL code is concluded in [3,4]. In [1] Re-use techniques is discussed, which is necessary in order to shorten the design cycle.…”

Section: IImentioning

confidence: 99%

“…At the time [2] summaries two simple generation method for checking connectivity of interface, the one is using a text editor by providing the formal to actual connections, the other is using script or program traverses the set of design modules, attempts to make connections based on specified rules. The method of checking Intellectual Property (IP) blocks is studied in [4,5].…”

Section: IImentioning

confidence: 99%

See 1 more Smart Citation

An Approach for Checking RTL Design Signal Sources and Destinations

Song¹,

Chen²,

Guo³

2017

Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)

View full text Add to dashboard Cite

Abstract-Formal check provides a method for detecting problems of SoC design in early time of verification. Looking at SoC design issues, most of design integration errors come from modules connectivity. Combining above two points, this paper descripts an approach check signal connectivity with formal check method. The approach parses Verilog HDL RTL code through a program, which writes by script language Perl, to analysis signals connectivity. It's helpful for both SoC designer and verification engineer.

show abstract

Cross-correlation of specification and RTL for soft IP analysis

Cited by 6 publications

References 0 publications

Hardware Trojans in Chips: A Survey for Detection and Prevention

Hardware Trojans in Chips: A Survey for Detection and Prevention

Ontology-guided Conceptual Analysis of Design Specifications

An Approach for Checking RTL Design Signal Sources and Destinations

Contact Info

Product

Resources

About