CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation

Ghosh, Swaroop; Bhunia, Swarup; Roy, Kaushik

doi:10.1109/tcad.2007.896305

Cited by 89 publications

(45 citation statements)

References 14 publications

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“…However, the enforced timing constraints for timing-error detection and the overheads for the applied recovery methods (e.g., multicycle replay penalties), especially in case of high activation probability of critical paths can offset the gains achieved by removing the static or dynamic safety margins. Alternative methods include the use of occasional two cycle operations, when operands are detected that activate the critical path in arithmetic units through delay prediction circuits [6]. Unfortunately, such a method can also lead to performance overheads in case of high excitation probability of the long latency paths and its application has so far been limited to arithmetic circuits.…”

Section: A Related Workmentioning

confidence: 99%

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Constantin

Wang

Karakonstantis

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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. (2015). Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. In ProceedingsDesign, Automation and Test in Europe, 2015 (pp. 381-386 Publisher rights © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. General rightsCopyright for the publications made accessible via the Queen's University Belfast Research Portal is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Abstract-Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28 nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

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Section: A Related Workmentioning

confidence: 99%

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Constantin

Wang

Karakonstantis

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…But this technique increases the delay of non-critical paths and these non-critical paths can become critical paths because of V th variation. Hence conventional design techniques to reduce power cannot be directly applied to future technology designs as power and variability pose opposite constraints [18]. To analyze the effect of inter-die and intra-die variations, we consider the 11-NAND2…”

Section: Thesis Organizationmentioning

confidence: 99%

An analytical approach to efficient circuit variability analysis in scaled CMOS design

Gummalla

Subramaniam

Cao

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ /µ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of V th variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing V th variation.

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“…Previous design-level optimizations for error-tolerant designs ( [12], [11]) identify and optimize critical paths that are frequently exercised during operation. BlueShift [12] identifies the most frequently violated timing paths during gate-level simulation, and optimizes the paths iteratively until the error rate is below the target.…”

Section: Introductionmentioning

confidence: 99%

“…CRISTA [11] isolates critical paths with Shannon-expansion-based partitioning. After partitioning, CRISTA downsizes cells on the critical path and upsizes cells on the non-critical paths: critical paths are made slower while non-critical paths are made faster.…”

Section: Introductionmentioning

confidence: 99%

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

Kahng

Kang

Kumar

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. The target error rate is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a design-level methodology that minimizes the power of a processor module for a target error rate. We show how this design-level methodology can be extended to design recovery-driven processors -processors that are optimized to take advantage of hardware or software error resilience. These may be single-core processors or heterogeneously-reliable multi-core processors, in which individual cores are optimized for different reliability targets. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of error rates to create soft processors -processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of error rates. We demonstrate significant power benefits over conventional design -11.8% on average over all modules and error rate targets, and up to 29.1% for individual modules. Processorlevel benefits are 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.ii ACKNOWLEDGMENTS

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CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation

Cited by 89 publications

References 14 publications

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

An analytical approach to efficient circuit variability analysis in scaled CMOS design

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

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