CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders

Abstract

To design the hardware for image signal processing pipelines in digital still cameras (DSCs) and video camcoders, it is a dilemma for conventional solutions, such as application-specific integrated circuits (ASICs) and digital signal processors (DSPs), to achieve high processing capability at low cost while maintaining high flexibility for various algorithms. With the observation of the characteristics of image signal-processing pipelines, including the different requirements for different operation modes and the algorithmic similarity of image-processing tasks, a new coarse-grained reconfigurable image stream processor (CRISP) is proposed in this paper. The design idea is to devote low-cost hardware for the requirements in the preview mode and add some hardware resources for higher flexibility and processing capability in the picture-taking mode. With the coarse-grained reconfigurable stage processing elements designed for image signal-processing tasks and the reconfigurable interconnection unit with unified communication protocol, CRISP can be reconfigured as an efficient dedicated hardware in the preview mode, and it can act like a flexible DSP for the picturetaking mode with different contexts. Implementation result shows that the core (die) size is 5 mm 2 (7.72 mm 2 ) with TSMC 0.18-m process, and the power consumption is 218 mW at 1.8 V. At the working frequency of 115 MHz, the processor is capable of processing 11 M-pixel still images at 10 fps for DSCs or 1920 1080 video frames at 55 fps for camcorders. CRISP can execute image pipelines 83 times faster than the state-of-the-art DSP with only about one-tenth die size.

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

“…The first solution is by reconfigurable ASIC. In paper [10], several kinds of reconfigurable stage processing elements (RSPE) are designed, trying to support algorithms which have similar characteristic of computation as much as possible. However, the datapath in each RSPE is fixed.…”

Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

“…3, the pixels in Window 1 occupy Slice 2 and Slice 3, and the pixels in Window 2 occupy Slice N. No matter what the window position is, the pixels required by the ISP never occupy the same bank in the HBDM. Based on the memory architecture of the HBDM, the traditional line buffer memory [17], which is used for window-based operations, can be saved to reduce hardware costs. Fig.…”

“…The ISP in the MLSoC is compared with the related work, the coarse-grained reconfigurable image stream processor (CRISP) [17], and the result is shown in Fig. 9(b), which shows that the proposed ISP uses 4.21 times of logic gate count to handle more than 11 times of input pixel bandwidth and to support 10.24 times of the maximum window size.…”

The eISP low-power and tiny silicon footprint programmable video architecture

“…Despite the computational efficiency of these solutions, they lack flexibility due to their hardwired implementation: only a few configurable parameters can be modified. Chen and Chien [4] proposes the CRISP architecture which can handle HD 1080p with low power consumption. Unfortunately, its flexibility is limited by its hard-wired embedded processes.…”