CRISP: A Template for Reconfigurable Instruction Set Processors

Beeck, Pieter Op De; Barat, Francisco; Jayapala, Murali; Lauwereins, Rudy

doi:10.1007/3-540-44687-7_31

Cited by 24 publications

(22 citation statements)

References 5 publications

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“…In this work, we have used the compilation and simulation capabilities provided by the CRISP framework [13]. It is a re-targetable compiler and simulator framework based on Trimaran [41], which is cycle accurate.…”

Section: Initial Vliw Architecturementioning

confidence: 99%

“…The baseline architecture described by CRISP [13] has been extended to support the power reduction mechanisms proposed in this paper. These modifications are described in the following paragraphs.…”

Section: Register File Hardware Modificationsmentioning

confidence: 99%

“…This minor hardware support provides a suitable mechanism to control the leakage energy consumed in the register file. Moreover, our results in a cycle-accurate Coarse-grained Reconfigurable Instruction Set Processor (CRISP) [13] show significant gains (up to 50%) while running realistic benchmarks from both the multimedia and wireless domains. Also, our techniques do not introduce any performance penalty and only a modest increase in silicon area.…”

Section: Introductionmentioning

confidence: 97%

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Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

Atienza

Raghavan

Ayala³

et al. 2008

Integration

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New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this new VLIW-based architectures, the register file is a very critical contributor to the overall power consumption and new approaches have to be proposed to reduce its power while preserving system performance. In this paper, we propose a novel joint hardware-software approach that reduces the leakage energy in the register files of these embedded VLIW architectures. This approach relies upon an energy-aware register assignment method and a hardware support that creates sub-banks in the global register file that can be switched on/off at run time. Our results indicate energy savings in the register file, after considering the overhead of the added extra hardware, up to 50% for modern multimedia embedded applications without performance degradation. We illustrate this approach using real-life applications running on these processors. We also illustrate the tradeoff between the area overhead vs. the gains in the leakage energy for the different strategies. r

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Section: Initial Vliw Architecturementioning

confidence: 99%

Section: Register File Hardware Modificationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

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Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

Atienza

Raghavan

Ayala³

et al. 2008

Integration

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“…The baseline VLIW architecture used in our work is provided by the CRISP framework [11] which is a cycle-accurate extension of the Trimaran framework [12] the following, the extensions applied to the CRISP framework are described.…”

Section: Variability-aware Hw/sw Compilationmentioning

confidence: 99%

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Raghavan

Ayala

Atienza³

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed variability of the RF proposing different compiletime and run-time design alternatives. The first alternative extends current RF architectures and uses a compile-time variability-aware register assignment algorithm. The second alternative presents a fully-adjustable pure run-time approach, which overcomes the variability loss as well, but at the extra cost of cycles and area. However, the savings achieved and the run-time management of the register delay variations without any support from the user, show a very promising application field. Our results in embedded system benchmarks show that variability can be tackled without significant performance penalty, and trade-offs between performance and area are possible thanks to the whole design spectrum provided by the two presented alternatives. I. INTRODUCTIONNew multimedia consumer applications require high performance embedded platforms due to their intensive processing requirements. In this area of embedded systems, Very Large Instruction Word (VLIW) processors provide a promising solution to achieve suitable performance-power trade-offs. However, transistor scaling in future technology nodes is accompanied by an increase of variability in process technology. Two types of variations exist: functional variation and parametric variation. Functional variation leads to loss in component functionality, while parametric variation leads to timing issues in the working component with respect to its originally designed speed [1], [2], [3].In this paper we present several solutions to handle parametric variation in shared register files of embedded VLIW processors, which provide also trade-offs of precharacterization (design time) effort and dynamic (run-time) overhead for self-tuning. The first solution (Section III) is a hardware/software (HW/SW) approach that relies on limited HW extensions in the Register File (RF), and a modified register assignment phase at compiler level to prevent using marked slow registers. In the latter two approaches (Section IV), we propose further extensions of the RF HW architecture to create completely run-time schemes against dynamic variation in the RF. These run-time approaches do

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“…This complete hardware/software approach enables reduction of the energy consumed in the register file of forthcoming embedded architectures with multiple processing elements without incurring in performance penalties. The experimental setup is built over the Coarse-grained Reconfigurable Instruction Set Processor (CRISP) framework (Op de Beeck et al, 2001), which provides the compilation and simulation capabilities.…”

Section: Introductionmentioning

confidence: 99%

Energy-aware compilation and hardware design for VLIW embedded systems

Ayala

López‐Vallejo

Atienza

et al. 2007

IJES

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Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

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CRISP: A Template for Reconfigurable Instruction Set Processors

Cited by 24 publications

References 5 publications

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Energy-aware compilation and hardware design for VLIW embedded systems

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