Credit-based dynamic reliability management using online wearout detection

Oliver, John; Amirtharajah, Rajeevan; Akella, Venkatesh; Chong, Frederic T.

doi:10.1145/1366230.1366258

Cited by 4 publications

(5 citation statements)

References 16 publications

(20 reference statements)

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“…We assume that each chip is equipped with an advanced builtin-self-test(BIST) module, that can detect faulty cores and capture performance variances when a device starts. Note that simple modules such as those introduced in [16], [6] can be easily incorporated into a multi-core platform for detecting purpose. The performance characteristics captured by the BIST module will be used to mirror the logical architecture to the underlying physical architecture with the goal of maximizing the application performance.…”

Section: Introductionmentioning

confidence: 99%

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Wang

Quan

Ren

et al. 2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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As transistor's feature size continues to scale down into the deep sub-micron domain, IC chip performance variation caused by manufacturing process becomes un-negligible and can cause significant discrepancies between an application's nominal design and its actual realization on individual manycore platforms. In this paper, we study the problem on how to reduce the total schedule length of a task graph when realizing its nominal design on individual Network-on-Chip(NoC) based many-core platform with faulty cores. Different from traditional approaches to re-define the mapping/scheduling decisions in the nominal design, our methods judiciously mirror the physical architecture of each individual platform to the logical platform, based on which the nominal design is conducted. To facilitate the phyical/logic architecture virtualization, we develop a performance metric based on the opportunity cost, a concept borrowed from the economics field. Three virtualization heuristics are presented in this paper. Our experimental results show that the proposed approach can achieve up to 30% with an average 15% performance improvement by taking advantage of the heterogeneity of each individual platform.

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Section: Introductionmentioning

confidence: 99%

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Wang

Quan

Ren

et al. 2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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“…Consequently, aging models were proposed to estimate the wear-out of non-critical systems, which do not require protection against transient faults, based on prior knowledge of the executed applications [30]. Unfortunately, the accuracy of the aging models is severely limited by unknown environmental conditions, manufacturing variations, unavailable technology information and insufficiently understood physics of some aging mechanisms [25].…”

Section: Introductionmentioning

confidence: 99%

“…In order to better cope with the inaccuracy of the aging models [25], self-tests performed concurrently with the normal operation may be used to improve the fault detection latency and the failure prediction capability [12] [28]. A way to avoid the impact on system performance is to execute these tests during idle periods.…”

Section: Introductionmentioning

confidence: 99%

Error prediction based on concurrent self-test and reduced slack time

Gherman

Massas

Evain

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency.Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent selftest of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.

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“…We assume that each chip is equipped with an advanced built-in-self-test(BIST) module, that can detect faulty cores and capture performance variances when a device starts. Note that simple modules such as those introduced in [129,94] can be easily incorporated into a multi-core platform for detecting purpose. The performance characteristics captured by the BIST module will be used to mirror the logical architecture to the underlying physical architecture with the goal of maximizing the application's performance.…”

Section: Related Workmentioning

confidence: 99%

“…Significant achievements have been made on layout techniques and other device technologies by adding built-in sensors or redundant devices [94,129,95]. However, it becomes increasingly challenging as transistor size scales towards dimensions close to or below 10 nm [154].…”

Section: Related Workmentioning

confidence: 99%

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

Wang¹

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To ensure timing constraints, traditional real-time system designs usually adopt a worst-case based deterministic approach. However, such an approach is becoming out of sync with the continuous evolution of IC technology and increased complexity of real-time applications. As IC technology continues to evolve into the deep submicron domain, process variation causes processor performance to vary from die to die, chip to chip, and even core to core. The extensive resource sharing on multicore platforms also significantly increases the uncertainty when executing real-time tasks. The traditional approach can only lead to extremely pessimistic, and thus, unpractical design of real-time systems.Our research seeks to address the uncertainty problem when designing real-time systems on multi-core platforms. We first attacked the uncertainty problem caused by process variation. We proposed a virtualization framework and developed techniques to optimize the system's performance under process variation. We further studied the problem on peak temperature minimization for real-time applications on multi-core platforms. Three heuristics were developed to reduce the peak temperature for real-time systems. Next, we sought to address the uncertainty problem vi in real-time task execution times by developing statistical real-time scheduling techniques. We studied the problem of fixed-priority real-time scheduling of implicit periodic tasks with probabilistic execution times on multi-core platforms. We further extended our research for tasks with explicit deadlines. We introduced the concept of harmonic to a more general task set, i.e. tasks with explicit deadlines, and developed new task partitioning techniques. Throughout our research, we have conducted extensive simulations to study the effectiveness and efficiency of our developed techniques.The increasing process variation and the ever-increasing scale and complexity of real-time systems both demand a paradigm shift in the design of real-time applications. Effectively dealing with the uncertainty in design of real-time applications is a challenging but also critical problem. Our research is such an effort in this endeavor, and we conclude this dissertation with discussions of potential future work.

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Credit-based dynamic reliability management using online wearout detection

Cited by 4 publications

References 16 publications

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Topology Virtualization for Throughput Maximization on Many-Core Platforms

Error prediction based on concurrent self-test and reduced slack time

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

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