Creation of Vias With Optimized Profile for 3‐D Through Silicon Interconnects (TSV)

Abstract

The continually growing functionality and pattern density of semiconductor devices leads to the development of innovative and cost‐effective 3‐D stacking and interconnection technologies for ICs and MEMS. These include the formation of vias for interconnects by deep reactive ion etch (DRIE) of silicon. The commonly used DRIE based on a Bosch patent creates holes with vertical sidewalls. However, holes with tapered sidewalls are advantageous, because their widened opening facilitates following deposition and filling processes and a bevelled upper edge of the vias prevents deposited layers from breaking. We created such holes by an optimized positive profile etching (PPE) process. Furthermore, we post‐treated holes with vertical sidewalls to eliminate the sharp edge at their opening and to widen this region. We created blind holes with tapered sidewalls with a diameter of 5–10 µm and through silicon holes with a diameter of 40 µm and aspect ratios up to 10.

Optimization of deep reactive ion etching for microscale silicon hole arrays with high aspect ratio

“…With the advantage of being able to fabricate high aspect ratio anisotropic patterns on silicon wafers [1,2], the deep reactive ion etching (DRIE) process has been extensively utilized for many applications including vias for 3D packaging [3,4] and microelectromechanical systems (MEMS) actuators [5,6] to name a few. Towards further miniaturization, high-density integration, and higher production yields, DRIE has been routinely adopted for realizing microscale trench and hole arrays with high aspect ratio [7].…”

Optimization of submicron deep trench profiles with the STiGer cryoetching process: reduction of defects

“…3D integration and 3D packaging have emerged during the last few years to minimize the dimensions and the cost of fabrication of the microcomponents: for example, 3D capacitors, realized in deep trenches, have started to replace planar geometries and through silicon vias are used for interconnections [1][2][3][4].…”