CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

Găitan, Vasile Gheorghiţă; Gaitan, Nicoleta Cristina; Ungurean, Ioan

doi:10.1109/tvlsi.2014.2346542

Cited by 39 publications

(66 citation statements)

References 28 publications

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“…The current paper extends the basic project presented by Gaitan et al in [5], proposing original new improvements for the nMPRA and nHSE. The aim of this project was to obtain a predictable architecture dedicated to small real-time applications.…”

Section: Discussionmentioning

confidence: 62%

“…With this new solution, the MEM/WB pipeline registers have reduced dimensions and memorize only one value to be written in the next stage. The dynamic nHSE is based on the remapping algorithm proposed by the nMPRA project in [5], being capable to perform fast task switching operations and to guarantee high performance in the execution of the pipeline assembly line.…”

Section: Pipeline and Thread Managementmentioning

confidence: 99%

“…The purpose of this paper is to continue and extends the nMPRA project presented by Gaitan et al in [5]. We present the experimental tests executed on a five stage pipeline architecture named nMPRA-MT (Multi Pipeline Register Architecture-Fine-grained Multithreading) [6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

Zagan¹

2015

IJCEE

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This paper conducts a thorough study of the schedulability and predictability questions for a custom designed CPU architecture, named Multi Pipeline Register Architecture (nMPRA). The nMPRA CPU implementation uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers, providing predictability and hardware-based isolation for hard real-time threads. We describe the real-time scheduling tests on nMPRA processor architecture, including also a fine-grained multithreading configuration. The present paper highlights several solutions to improve the performance of CPU architectures and to overcome the overhead inconveniences of the Operating Systems.

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Section: Discussionmentioning

confidence: 62%

Section: Pipeline and Thread Managementmentioning

confidence: 99%

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Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

Zagan¹

2015

IJCEE

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“…In order to address questions and problems related to current RTS, this paper validates the treatment of multiple events by the nMPRA processor [3], thus demonstrating the functionality and the real time performances of the integrated scheduler and the flexibility of the nMPRA processor. This paper is structured as follows: the first section contains a brief introduction, and section two describes the nMPRA processor architecture; section III addresses the implementation in hardware of the mechanism of treating multiple events; the experimental results thus obtained will be analyzed and discussed in section IV; section V presents related work and the paper ends with the final conclusions in section VI.…”

Section: Introductionmentioning

confidence: 81%

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

Zagan¹,

Gaitan²,

Găitan³

2017

ijacsa

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Abstract-One of the fundamental requirements of real time operating systems is the determinism of executing critical tasks and treating multiple periodic or aperiodic events. The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization and inter-task communication mechanisms. Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental results obtained using Virtex-7 FPGA circuit. The article's element of originality is the very short response time required in treating and prioritizing events.

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“…Based on these constraints, in recent years, there has been intensive research on hardware scheduling of real-time systems. Among the many approaches regarding software and hardware scheduled [2][3] [4][5] [6], the actual implementations must provide hardware based isolation by means of a real-time operating system. While the commercial RTOS reduce significantly the hardware costs, these new approaches must be verified and certified, a process which is not simple since the system introduces overhead for task switching and execution time monitoring.…”

Section: Introductionmentioning

confidence: 99%

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

Gaitan¹,

Zagan²,

Găitan³

2015

ijacsa

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Abstract-The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.

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CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

Cited by 39 publications

References 28 publications

Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating

Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation

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