Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC

Abstract

The confluence of technology trends and economics has reincarnated computer architecture and specifically, softwarehardware co-design. We are entering a new era of a completely open ecosystem, from applications to chips and everything in between. The software-hardware co-design of supercomputers for tomorrow requires flexible tools today that will take us to the Exascale and beyond. The MareNostrum Experimental Exascale Platform (MEEP) addresses this by proposing a flexible FPGAbased emulation platform, designed to explore hardware-software co-designs for future RISC-V supercomputers. This platform is part of an open ecosystem, allowing its infrastructure to be reused in other projects. MEEP's inaugural emulated system will be a RISC-V based self-hosted HPC vector and systolic array accelerator, with a special aim at efficient data movement. Early development stages for such an architecture require fast, scalable and easy to modify simulation tools, with the right granularity and fidelity, enabling rapid design space exploration. Being a part of MEEP, this paper introduces Coyote, a new open source, execution-driven simulator based on the open source RISC-V ISA and which can provide detailed insights at various levels and granularities. Coyote focuses on data movement and the modelling of the memory hierarchy of the system, which is one of the main hurdles for high performance sparse workloads, while omitting lower level details. As a result, performance evaluation shows that Coyote achieves an aggregate simulation of up to 6 MIPS when modelling up to 128 cores. This enables the fast comparison of different designs for future RISC-V based HPC architectures.

RISC-V Instruction Set Architecture Extensions: A Survey

“…It combines a 16-stage deep pipeline with multi-issue Out-of-Order execution, and it can scale up to 64 clusters, 512 cores and 1,024 harts/threads. The Spain Barcelona Supercomputing Center explored software-hardware co-design of supercomputers based on RISC-V [31]. RISC-V also promotes the open source of high-performance processors (such as CPUs).…”