Coverage directed test generation for functional verification using bayesian networks

Fine, Shai; Ziv, Avi

doi:10.1145/775905.775907

Cited by 43 publications

(57 citation statements)

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“…These solutions mainly focus on ways to transform the coverage information into constraints / biases / directives for the random test generator. These include model checking ( [9], [10]) and machine-learning ( [11], [12], [13], [14]) based approaches. All of these, however, are geared towards single processors and do not present effective ways for collecting coverage for shared memory multi-processors.…”

Section: Related Workmentioning

confidence: 99%

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Mammo

Larimer

Morgan

et al. 2012

2012 13th International Workshop on Microprocessor Test and Verification (MTV)

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Abstract-Functional coverage plays a pivotal role in assuring the quality of input stimuli used in the verification of modern digital designs. For an out-of-order multi-processor design, simulation of a detailed model of the design is often required to observe relevant design behaviors for functional coverage. However, since such a model is not available during the early phases of test development, verification teams are forced to wait until much later in the verification process to evaluate the quality of their test cases. Even then, the quality of the tests can be assured only on one specific design implementation -an undesirable characteristic for test and regression suites that are meant to be used across multiple generations and/or implementations of an architecture. This work addresses this issue by presenting a novel, implementation-independent, execution tracebased, coverage collection solution. Our solution enables the early evaluation of multi-processor tests using a high-level model of a design. In addition, it can be deployed with detailed design models, if desired, for further analysis alongside implementationspecific coverage models.

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Section: Related Workmentioning

confidence: 99%

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Mammo

Larimer

Morgan

et al. 2012

2012 13th International Workshop on Microprocessor Test and Verification (MTV)

View full text Add to dashboard Cite

show abstract

“…Most of them employ coverage-directed test generation processes, as in StressTest, but use sophisticated techniques to relate input generation to coverage, such as Bayesian networks and computer learning approaches [7]. Some of these other engines are aimed specifically at register-level representations of a design, and focus on tag coverage [15] instead of functional coverage as StressTest.…”

Section: Background and Prior Workmentioning

confidence: 99%

“…Some of these techniques involve the use of program templates which define the structure of the desired test, along with primitives to control the randomization of the related data, such as opcodes, register operands, and memory addresses [1], [3], [8], [12], [17]. Improvements on these baseline techniques use coverage metrics to drive the generation of the test programs either through Markov models [15] (as in our solution) or with Bayesian networks [7].…”

mentioning

confidence: 99%

Microprocessor Verification via Feedback-Adjusted Markov Models

Wagner

Bertacco

Austin

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex microarchitectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often, size does not seem to matter in verification, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a novel closed-loop simulation-based approach to hardware verification and present a tool called StressTest that uses our methods to locate hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-model-driven random instruction generator with activity monitors. The model is generated from the user-specified template files and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity nodes within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the user-selected points of interest. In parallel, StressTest monitors the correctness of the DUT response and, if the design behaves against expectation, it reports a bug and a trace leading to it. Using two microarchitectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.

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“…Simulationbased verification tries to uncover errors of design by detecting circuits' faulty behavior when deterministic or pseudo-random simulation vectors are applied. Many practices involve in technologies to improve test generation and coverage analysis [2][3] [4]. Some papers are more concerned with comparison among those advanced techniques within existing strategies of test generation.…”

Section: Introductionmentioning

confidence: 99%

EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores

Shen

Chen

Huang

2005

Embedded Software and Systems

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Abstract:Core-based system-on-chip (SoC) design is quickly becoming a new paradigm in electronic system design due to the reusability of IP cores. However, the validation of IP cores is the most time consuming task in the design flow. This paper presents EmGen, an automatic test-program generation tool designed for embedded microprocessor cores. EmGen provides an configurable formal specification model with heuristic knowledge, which can generate test programs according to different configuration of microprocessors' architecture, a test generation scheme based on heuristic algorithms, which can efficiently provide instructions in test programs, and validation testbenches, which support simulation with generated test programs automatically and check the equivalence of microprocessors and the specified instruction reference model. EmGen is currently in use at ICT for the verification of embedded microprocessor cores. Experiments results show that EmGen can improve verification process and cut down skilled manpower obviously.

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Coverage directed test generation for functional verification using bayesian networks

Cited by 43 publications

References 0 publications

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Microprocessor Verification via Feedback-Adjusted Markov Models

EmGen: An Automatic Test-Program Generation Tool for Embedded IP Cores

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