Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

Abstract

The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept

Resilient routing implementation in 2D mesh NoC

“…Most routing implementation techniques that have been proposed to efficiently capture the routing function for irregular topologies are either table based [6][7][8] or require a complex constrained switch design [9]. This fact motivates us to design an efficient routing implementation technique to address irregular topologies.…”

“…Though ARIADNE provides an area improvement over Immunet, its underlying routing algorithm is not optimized for regular networks. Thus, solutions based on forwarding tables are flexible for irregular topologies but suffer from the scalability and high cost associated with tables [9]. 3.…”

“…To support this, Rodrigo et al [9] presented Universal Logic Based Distributed Routing (uLBDR). uLBDR ensures complete reachability by packet replication at two output ports which leads to a few design constraints on the network switch.…”

“…Recently, uLBDR (Universal Logic Based Distributed Routing) [9] has been proposed as a scalable and efficient routing implementation method to support irregular 2D mesh topologies. It combines the scalability of traditional FSM based implementations and the flexibility of table-based implementations.…”

Floorplan-Aware High Performance NoC Design

“…In order to increase performance (higher throughput and/or lower latencies) several techniques have been proposed that can be applied to the canonical switch design. Some techniques focus on specific parts of the switch as routing [86], arbitration [17], or crossbar [47]. Some of these modify switch pipelining shown in Figure 3.1(b) by performing some stages in parallel.…”