Resilient routing implementation in 2D mesh NoC

Abstract

With the rapid shrinking of technology and growing integration capacity, the probability of failures in Networks-on-Chip (NoCs) increases and thus, fault tolerance is essential. Moreover, the unpredictable locations of these failures may influence the regularity of the underlying topology, and a regular 2D mesh is likely to become irregular. Thus, for these failure-prone networks, a viable routing framework should comprise a topology-agnostic routing algorithm along with a cost-effective, scalable routing mechanism able to handle failures, irrespective of any particular failure patterns. Existing routing techniques designed to route irregular topologies efficiently lack flexibility (logic-based), scalability (table-based) or relaxed switch design (uLBDR-based). Designing an efficient routing implementation technique to address irregular topologies remains a pressing research problem. To address this, we present a fault resilient routing mechanism for irregular 2D meshes resulting from failures. To handle irregularities, it avoids using routing tables and employs a few fixed configuration bits per switch resulting in a scalable approach. Experiments demonstrate that the proposed approach is guaranteed to tolerate all locations of single and double-link failures and most multiple failures. Also, unlike uLBDR it is not restricted to any particular switching technique and does not replicate any extra messages. Along with fault tolerance, the proposed mechanism can achieve better network performance in fault-free cases. The proposed technique achieves graceful performance degradation during failure. Compared to uLBDR, our method has 14% less area requirements and 16% less overall power consumption.

Efficient Design and Fpga Implementation of Microarchitecture for Network-On-Chip Routers

“…Creating proficient channels is generally a circuit plan issue [14,20,[25][26][27]; interestingly, a switch's execution, cost and effectiveness essentially rely upon its microarchitecture. The present thesis researches usage viewpoints and microarchitectural configuration exchange offs for proficient superior NoC switches.…”

Isolated Routing Algorithm without Virtual Channels for Network-on-Chip

“…然 而, 该算法只适用于规则拓扑子网, 会导致更多网 络碎片, 从而降低芯片利用率. 目前针对不规则拓 扑子网的隔离路由算法研究较少, 最常用的是基 于逻辑的分布式路由(logic based distributed routing, LBDR)算法 [7] , 其具有足够的可伸缩性和灵活 性, 以适应不规则网络. 然而, LBDR 算法只支持 最小路径路由, 当不规则拓扑网络不能满足最小 路径路由时, 该算法失效.…”

“…为了解决上述问题, 本文采用区域拓扑模型 识别不规则子网, 并且结合已有研究成果的容错 奇 偶 (fault-tolerant odd-even, FTOE) 转 向 模 型 [16] , 提出了一种低开销的隔离路由算法(low-cost isolation routing algorithm, LIRA [7] 算法)和 TPDOR [15] 算法与之进行比较.…”