Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2014

Self Cite

This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, t rem and t mod , with sets of detected faults D rem and D mod , respectively. Starting from t new = t mod , and considering t new as a variation of t rem , the procedure restores bits of t rem into t new as necessary to ensure that faults from D rem are detected by t new . The procedure then restores bits of t mod into t new as necessary to ensure that all the faults from D mod are detected by t new . The test t new is used for replacing t mod , and the faults it detects out of D rem are moved to D mod . After several such steps, if D rem becomes empty, t rem can be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification.

Section: Introductionmentioning

confidence: 99%

Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2014

Self Cite

“…We prepared two kinds of test sets for each circuit as an initial test set: an uncompacted test set and a compacted test set [6]. Table 5 and Table 6 show results for uncompacted test sets and Table 7 and Table 8 show results for compacted test sets.…”

Section: Resultsmentioning

confidence: 99%

“…2. In order to ensure that T' would cover T and that the fault coverage of 1 would be the same as that of T, the essential faults of ti in T must be detected by ti' in 1, where an essential fault is a fault detected by vector ti but not detected by any other test vector in T. Essential faults can be identified by fault simulation based on double detection [6]. Non-essential faults of ti do not have to be detected by ti' because they have the opportunity to be detected by another test vector.…”

Section: Don't Cares Oftest Vectorsmentioning

confidence: 99%

See 1 more Smart Citation

Don't-care identification on specific bits of test patterns

Miyase¹,

Kajihara²,

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

et al.

Given a test set for stuck-at faults, a primary input value may be changed to the opposite logic value without losing fault coverage. One can regard such a value as a don 't-care (X). The don't care values can be filled appropriately to achieve test compaction, test data compression, or power reduction during testing. Howevel; these uses are better served if the don't cares can be placed in desired/specific bit positions of the test patterns. In this papel; we present a methodfor maximally fixing Xs on specific bits of given test vectors. Experimental results on ISCAS benchmark circuits show how the proposed method can increase the number of Xs on specific bits compared with an earlier proposed method.

“…For ISCAS-89 benchmark circuits, we used the combinational test sets from [9], and test sequences compacted by the static compaction procedure of [10]. For ITC-99 benchmark circuits, the combinational test sets were selected out of a large set of random patterns, and the test sequences were the ones generated by PROPTEST [11].…”

Section: Resultsmentioning

confidence: 99%

Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

16th International Conference on VLSI Design, 2003. Proceedings.

Reddy²

We propose a new static compaction procedure for scan circuits that generates a test set with a reduced test application time. The proposed procedure combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with short primary input sequences, and one that tends to generate small numbers of tests with long primary input sequences. The proposed procedure starts from a test set with a large number of tests and long primary input sequences, and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time.