Correlation power analysis attack against STT-MRAM based cyptosystems

Chakraborty, Abhishek; Mondal, Ankit; Srivastava, Ankur

doi:10.1109/hst.2017.7951835

Cited by 25 publications

(14 citation statements)

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“…(i) High write current: This can lead to supply noise. Adversary can generate deterministic supply noise and launch a DoS attack [85], fault injection attack [85], information leakage attack [86], and row hammer attack [87]; (ii) Asymmetric [49] write and read current: This can be leveraged to launch side channel attack [81][82][83][84]; (iii) Susceptibility to external fields: An external magnetic field can lead to magnetic orientation flip of MTJ free layer of MTJ which corrupts the data [80]. Adversary can leverage this to launch attacks (e.g., DoS).…”

Section: Nvm Devices and Their Vulnerabilitiesmentioning

confidence: 99%

“…The results show that the secret key can be retrieved from MRAM write operation traces. In [83], a correlation power analysis (CPA) on MRAM write operation was performed. The work proposes a hypothetical power model that considers the difference of 0 → 1 and 1 → 0 transitions to estimate the post-alignment power consumption while writing to MRAM.…”

Section: Sca On Sttrammentioning

confidence: 99%

“…Everspin lists the maximum magnetic tolerance for their MRAM chips during write/read/standby to be only ~100 Oe [47]. High and asymmetric write current [79] and long and asymmetric write latency [80] (common in most NVMs) can serve as side channels exposing the number of '1's and '0's in a memory word, weakening the data privacy [80][81][82][83][84].…”

Section: Introductionmentioning

confidence: 99%

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Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Khan

Ghosh

2021

JLPEA

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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Section: Nvm Devices and Their Vulnerabilitiesmentioning

confidence: 99%

Section: Sca On Sttrammentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Khan

Ghosh

2021

JLPEA

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“…4.1 Common SCA simulations Common SCA can be divided into Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) [11,12]. CPA can be further classified into sub-types due to different leakage models.…”

Section: Simulation Of Side-channel Attackmentioning

confidence: 99%

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance

Zou

Cui

Dai

et al. 2021

IEICE Electron. Express

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An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. To reduce the area and power, two Substituting Byte blocks (S-Boxes) are reused in key expansion and the data encryption module, respectively. To mitigate SCA, we adopt asynchronous dual-rail logic with dual-rail balanced logic and new dual-rail spacer latch. Common and Machine learning (ML) SCA simulations are performed to validate SCA resistance. To the best of our knowledge, we are the first ones to perform the ML SCA evaluations on asynchronous AES. Simulation results with 200K power traces demonstrate that our asynchronous AES is immune to the attacks. Our proposed asynchronous AES occupies an area of 0.016 2 in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V.

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“…Power analysis attack is one of the side-channel attack, where the attacker monitors the power consumption of the cryptographic device without making any physical changes to the device [9,12]. In the recent years, researchers have focused on the security evaluation of Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) against power analysis attack [3,6,17]. However, there is no security evaluation of hybrid CMOS/MTJ circuits against power analysis attack.…”

Section: Introductionmentioning

confidence: 99%

Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design

2021

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Hybrid MTJ/CMOS-based Logic-in-Memory (LiM) architecture-based circuits show high potential in designing low-power circuits by reducing the leakage power. In this work, we have proposed a novel energy-efficient and Secure MTJ/CMOS Logic (SMCL) circuits to design ultra-low-power and DPA-resistant MTJ/CMOS circuits. Similar to the existing MTJ/CMOS designs, the proposed MTJ/CMOS design also works in two different modes of clock. The proposed MTJ/CMOS designs have considerable power savings during the pre-charge of the clock. During the pre-charge phase, both output nodes are precharged to VDD/2, while during the evaluate phase, one node will be charged to VDD, while the other node will discharged to ground. Moreover, the proposed SMCL consumes uniform power by masking the MTJ during the write operation from the power supply, thereby thwarting the power analysis-based side-channel attacks. From our simulations, we have observed that the proposed SMCL-based PRESENT-80 cryptographic hardware has about 42% and 59% of energy savings as compared to the PCSA-based MTJ/CMOS and conventional CMOS-based implementation. Furthermore, we have also performed the DPA attack on the SMCL-based PRESENT-80 and the secret key was not revealed after 16,000 power traces.

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Correlation power analysis attack against STT-MRAM based cyptosystems

Cited by 25 publications

References 0 publications

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance

Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design

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