Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design

Abstract

Hybrid MTJ/CMOS-based Logic-in-Memory (LiM) architecture-based circuits show high potential in designing low-power circuits by reducing the leakage power. In this work, we have proposed a novel energy-efficient and Secure MTJ/CMOS Logic (SMCL) circuits to design ultra-low-power and DPA-resistant MTJ/CMOS circuits. Similar to the existing MTJ/CMOS designs, the proposed MTJ/CMOS design also works in two different modes of clock. The proposed MTJ/CMOS designs have considerable power savings during the pre-charge of the clock. During the pre-charge phase, both output nodes are precharged to VDD/2, while during the evaluate phase, one node will be charged to VDD, while the other node will discharged to ground. Moreover, the proposed SMCL consumes uniform power by masking the MTJ during the write operation from the power supply, thereby thwarting the power analysis-based side-channel attacks. From our simulations, we have observed that the proposed SMCL-based PRESENT-80 cryptographic hardware has about 42% and 59% of energy savings as compared to the PCSA-based MTJ/CMOS and conventional CMOS-based implementation. Furthermore, we have also performed the DPA attack on the SMCL-based PRESENT-80 and the secret key was not revealed after 16,000 power traces.

Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security

“…The thermal stability factor needs to be optimized to ensure proper operation during temperature sweep tests in the system-on-chip (SoC) design flow. In [29], a hybrid CMOS/MTJ circuit for low power design has been discussed with significant improvement in circuit parameters. Adding a logic locking block using an MTJ-based AND gate will cause an area overhead, but MTJ devices have competitive bit area cell, and improvement in scaling for such devices in the future may decrease the required area overhead.…”