1993
DOI: 10.1149/1.2056094
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Correlation of 150 mm P/P+ Epitaxial Silicon Wafer Flatness Parameters for Deep Submicron Applications

Abstract: Experimental data for 426 P/P* epitaxial wafers from two suppliers are presented for both front-surface and back-surface site flatness parameters SFQR, SFQD, SBIR, SBID and global data GFLR, GFLD, GF3R, GF3D, GBIR, taper, bow, warp, and sort. Correlations and recommendations among the various flatness parameters are presented to gain insight into the characterfstic flatness parameters required for an accurate description of wafer flatness. The recommended flatness parameters for measurement are GFLR, GBIR, SFQ… Show more

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“…These applications, all of which involve brittle materials have provided new and even more difficult challenges in achieving the appropriate "surface finish." [3][4][5][6][7][8] In the case of VLSI applications for instance, as device and interconnect feature sizes are continually scaled down, the delay associated with interconnect resistance and capacitance becomes the single most dominant feature of the delay associated with signal propagation. Hence, a critical component of integrated silicon technology is on the multilevel interconnection process.…”
Section: Introductionmentioning
confidence: 99%
“…These applications, all of which involve brittle materials have provided new and even more difficult challenges in achieving the appropriate "surface finish." [3][4][5][6][7][8] In the case of VLSI applications for instance, as device and interconnect feature sizes are continually scaled down, the delay associated with interconnect resistance and capacitance becomes the single most dominant feature of the delay associated with signal propagation. Hence, a critical component of integrated silicon technology is on the multilevel interconnection process.…”
Section: Introductionmentioning
confidence: 99%