2001
DOI: 10.1063/1.1341230
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Correlation between leakage current density and threading dislocation density in SiGe p-i-n diodes grown on relaxed graded buffer layers

Abstract: A correlation between bulk leakage current density and threading dislocation density in silicon–germanium mesa-isolated diodes fabricated on relaxed graded buffer layers is presented. Si0.75Ge0.25 p-i-n diodes were grown on SiGe graded buffers with different grading rates. Graded buffers with different grading rates yielded “virtual substrates” with varying densities of threading dislocations. Bulk leakage current densities were differentiated from surface leakage currents by using p-i-n diodes with different … Show more

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Cited by 174 publications
(89 citation statements)
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“…2). Qualitatively these images are very similar to those obtained previously [4,10,11], where they were associated with bunches of misfit dislocations. It should be noted that in both structures the EBIC images obtained in the same place at different energies reveal practically the same structure (Fig.…”
Section: Resultssupporting
confidence: 75%
See 2 more Smart Citations
“…2). Qualitatively these images are very similar to those obtained previously [4,10,11], where they were associated with bunches of misfit dislocations. It should be noted that in both structures the EBIC images obtained in the same place at different energies reveal practically the same structure (Fig.…”
Section: Resultssupporting
confidence: 75%
“…Therefore, a partial strain relaxation could occur during subsequent thermal processing resulting in formation of the misfit dislocations at the strained-Si/SiGe interface. The misfit and threading dislocations in the strained Si layer can essentially affect the device performance [4][5][6]. An additional factor affecting the device performance is the cross-hatching, a large-scale roughness inherent in such structures due to the stress fields associated with the underlying misfit dislocations generated during relaxation in the graded SiGe layer [7].…”
Section: Introductionmentioning
confidence: 99%
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“…During the device processing, such as the post-growth annealing and ion implantation of a strained silicon layer, the strain begins to relax via the generation of defects, especially misfit/threading dislocations, and Ge interdiffusion, which degrade the device performance by decreasing the charge mobility and increasing the leakage current [5][6][7][8]. Since threading dislocations (TDs) have a major influence upon device performance, many alternative processes for reducing their density have been suggested [9,10]. As the misfit dislocation density depends on the materials involved, it will be mainly determined by the lattice mismatch and different thermal coefficients rather than the growth condition due to its intrinsic nature.…”
Section: Introductionmentioning
confidence: 99%
“…5 However, many of these device architectures rely on latticemismatched epitaxy, for which threading dislocations are inevitable. Because these dislocations act as recombination centers for charge carriers [6][7][8] and reduce the device efficiency, the density of dislocations in the active region of the device must be minimized, generally by carefully varying the lattice constant in a thick graded layer. [9][10][11] It may also be possible to mitigate the impact of these dislocations via passivation with impurities, [12][13][14][15] or by controlling the type 16 or direction of the remaining dislocations.…”
Section: Introductionmentioning
confidence: 99%