Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware

Didier, Keryan; Potop-Butucaru, Dumitru; Iooss, Guillaume; Cohen, Albert; Souyris, Jean; Baufreton, Philippe; Graillat, Amaury

doi:10.1145/3328799

Cited by 11 publications

(9 citation statements)

References 47 publications

(77 reference statements)

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“…Not only because of the potential efficiency loss, but because in many cases the implementation must have a different structure. For instance, in avionics MIF/MAF applications [10] the implementation must have a structure similar to that of Figure 6 (left), where a global periodic pattern (the global loop, named major frame, or MAF) is split by the tick operations into time intervals of equal length (the minor frames, or MIFs), each containing a different code.…”

Section: Compilationmentioning

confidence: 99%

“…This operational mechanism, whose formal semantics is defined in Section 3.5, can be easily implemented on various execution platforms ranging from low-level timers on bare metal platforms [10] to POSIX system services such as longjmp (as we do in Section 5) to coroutine mechanisms of various languages and to RTOS services such as PERIODIC_WAIT in the avionics-oriented IMA/ARINC 653 standard [1].…”

Section: Compilationmentioning

confidence: 99%

“…Consider a non-reactive SSA function 9 f and consider the result f of replacing all instances of undef in f with values of Int * \ {⊥} or with other variables (without breaking dominance). 10 Consider an initial execution state s 0 and an execution trace s 0 → • • • → s n of f that does not block. Then, there exists a unique trace…”

Section: Compilation Of Undefmentioning

confidence: 99%

“…Thus, computations driven by the output of the LSTM are executed at a pace five times slower than the internal computations of the LSTM (grouped in node @lstm). Such multi-rate execution mechanisms are also common in embedded control applications specified in Lustre, and can be used to support multi-period execution [10].…”

Section: Neural Network Use Casesmentioning

confidence: 99%

“…Memory allocation for synchronous languages also poses other challenges, such as the fact that modular code generation requires in the general case an inefficient encoding for memory constructs, which uses not one, but two variables for each state element. Several papers address this issue in previous work[10,11]. ACM Transactions on Architecture and Code Optimization, Vol.…”

mentioning

confidence: 99%

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Weaving Synchronous Reactions into the Fabric of SSA-form Compilers

Pompougnac

Beaugnon²,

Cohen³

et al. 2022

ACM Trans. Archit. Code Optim.

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We investigate the programming of reactive systems combining closed-loop control with performance-intensive components such as Machine Learning (ML). Reactive control systems are often safety-critical and associated with real-time execution requirements, a domain of predilection for synchronous programming languages. Extending the high levels of assurance found in reactive control systems to computationally intensive code remains an open issue. We tackle it by unifying concepts and algorithms from synchronous languages with abstractions commonly found in general-purpose and ML compilers. This unification across embedded and high-performance computing enables a high degree of reuse of compiler abstractions and code. We first recall commonalities between dataflow synchronous languages and the static single assignment (SSA) form of general-purpose/ML compilers. We highlight the key mechanisms of synchronous languages that SSA does not cover—denotational concepts such as synchronizing computations with an external time base, cyclic and reactive I/O, as well as the operational notions of relaxing control flow dominance and the modeling of absent values. We discover that initialization-related static analyses and code generation aspects can be fully decoupled from other aspects of synchronous semantics such as memory management and causality analysis, the latter being covered by existing dominance-based algorithms of SSA-form compilers. We show how the SSA form can be seamlessly extended to enable all SSA-based transformations and optimizations on reactive programs with synchronous concurrency. We derive a compilation flow suitable for both high-performance and reactive aspects of a control application, by embedding the Lustre dataflow synchronous language into the SSA-based MLIR/LLVM compiler infrastructure. This allows the modeling of signal processing and deep neural network inference in the (closed) loop of feedback-directed control systems. With only minor efforts leveraging the MLIR infrastructure, the generated code matches or outperforms state-of-the-art synchronous language compilers on computationally intensive ML applications.

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Section: Compilationmentioning

confidence: 99%

Section: Compilationmentioning

confidence: 99%

Section: Compilation Of Undefmentioning

confidence: 99%

Section: Neural Network Use Casesmentioning

confidence: 99%

mentioning

confidence: 99%

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Weaving Synchronous Reactions into the Fabric of SSA-form Compilers

Pompougnac

Beaugnon²,

Cohen³

et al. 2022

ACM Trans. Archit. Code Optim.

Self Cite

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Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks

Carle

Cassé

2021

Architecture of Computing Systems

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Synthesis of Parallel Software from Heterogeneous Dataflow Models

Rafique

Schneider

2022

SN COMPUT. SCI.

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Dataflow process networks (DPNs) are intrinsically data-driven, i.e., node actions are not synchronized among each other and may fire whenever sufficient input operands arrived at a node. While the general model of computation (MoC) of DPNs does not impose further restrictions, many different subclasses of DPNs representing different dataflow MoCs have been considered over time. These classes mainly differ in the kinds of behaviors of the processes. A DPN may be heterogeneous in that different processes in the network belong to different classes of DPNs. A heterogeneous DPN can therefore be effectively used to model and to implement different components of a system with different kinds of processes and, therefore, different dataflow MoCs. This paper presents a model-based design based on different dataflow MoCs including their heterogeneous combinations. In particular, it covers the automatic software synthesis of systems from DPN models. The main objective is to validate, evaluate and compare the artifacts exhibited by different dataflow MoCs at the implementation level of systems under the supervision of a common design tool. Moreover, this work also offers an efficient synthesis method that targets and exploits heterogeneity in DPNs by generating implementations based on the kinds of behaviors of the processes. The proposed synthesis method provides a tool chain including different specialized code generators for specific dataflow MoCs, and a runtime system that finally maps models using a combination of different dataflow MoCs on cross-vendor target hardware.

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Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware

Cited by 11 publications

References 47 publications

Weaving Synchronous Reactions into the Fabric of SSA-form Compilers

Weaving Synchronous Reactions into the Fabric of SSA-form Compilers

Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks

Synthesis of Parallel Software from Heterogeneous Dataflow Models

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