Synthesis of Parallel Software from Heterogeneous Dataflow Models

Abstract

Dataflow process networks (DPNs) are intrinsically data-driven, i.e., node actions are not synchronized among each other and may fire whenever sufficient input operands arrived at a node. While the general model of computation (MoC) of DPNs does not impose further restrictions, many different subclasses of DPNs representing different dataflow MoCs have been considered over time. These classes mainly differ in the kinds of behaviors of the processes. A DPN may be heterogeneous in that different processes in the network belong to different classes of DPNs. A heterogeneous DPN can therefore be effectively used to model and to implement different components of a system with different kinds of processes and, therefore, different dataflow MoCs. This paper presents a model-based design based on different dataflow MoCs including their heterogeneous combinations. In particular, it covers the automatic software synthesis of systems from DPN models. The main objective is to validate, evaluate and compare the artifacts exhibited by different dataflow MoCs at the implementation level of systems under the supervision of a common design tool. Moreover, this work also offers an efficient synthesis method that targets and exploits heterogeneity in DPNs by generating implementations based on the kinds of behaviors of the processes. The proposed synthesis method provides a tool chain including different specialized code generators for specific dataflow MoCs, and a runtime system that finally maps models using a combination of different dataflow MoCs on cross-vendor target hardware.

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

“…If they are mapped onto the same SPE. They cannot overlap, obeying the execution sequence shown in (18). M axvalue is a very large value, and the inequality should be satisfied when o ik is 1. o ik is calculated using the inequality (19), which means that if both r ik and j y ijk are 1, o ik is 1; otherwise, it is 0.…”

“…[7] used the tool to parallelize a PID control model with multiple rates on MPSoC with FPGA. [18] generated parallel codes for heterogeneous dataflow process networks (DPNs).…”