Copper-Based TSV: Interposer

Killge, Sebastian; Neumann, Volker; Bartha, Johann W.

doi:10.1007/978-3-319-20481-9_2

Cited by 5 publications

(9 citation statements)

References 13 publications

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“…1. Plasma-induced deposition of a polymeric layer as passivation layer using C 4 F 8 as working gas [18].…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

“…2. Anisotropic removal of passivation layer on the bottom followed by an isotropic Si chemical etch, and SF 6 is usually employed as working gas for etching of Si [18].…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

“…Followed by the etching step, a deposition step is performed for a few seconds to coat the overall polymeric passivation layer (Figure 6d), which is similar to the first step. Then the etching step is repeated (Figure 6e), which is similar to step 2 and step 3 [18]. The removal of passivation layer on vertical surfaces is much faster than on horizontal, since the ions are accelerated in vertical direction.…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

“…The removal of passivation layer on vertical surfaces is much faster than on horizontal, since the ions are accelerated in vertical direction. After the removal of passivation layer on the trench bottom, the further etchants start etching the trench bottom, and simultaneously polymeric passivation layer of the sidewall slows the lateral etch rate [18]. To achieve the desired depth of TSVs, these etching and deposition steps are repeated several times (Figure 6f) [18].…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

“…After the removal of passivation layer on the trench bottom, the further etchants start etching the trench bottom, and simultaneously polymeric passivation layer of the sidewall slows the lateral etch rate [18]. To achieve the desired depth of TSVs, these etching and deposition steps are repeated several times (Figure 6f) [18]. The DRIE process involves six steps, and the performance of each step is controlled by a significant number of parameters such as gas flows, the power of the inductively coupled plasma or the platen source, time, etc.…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

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Silicon-Based Micromachining Process for Flexible Electronics

Yang¹,

Wu²

2019

Micromachining

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In this chapter, we introduce silicon-based micromachining process and devices for flexible electronics application. Silicon-based flexible electronics have the unique advantage over other polymer-based process that leverage the traditional standard CMOS process and can be integrated with scalable IC technology. While integrating with CMOS process, special considerations must be taken into account, such as release process, transfer process, and process integration, in order to produce siliconbased flexible electronics. Several efforts and process developments will be illustrated in this chapter with the highlights of imager and wearable electronics application.

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“…1. Plasma-induced deposition of a polymeric layer as passivation layer using C 4 F 8 as working gas [18].…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

“…2. Anisotropic removal of passivation layer on the bottom followed by an isotropic Si chemical etch, and SF 6 is usually employed as working gas for etching of Si [18].…”

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

Section: Deep Reactive-ion Etchingmentioning

confidence: 99%

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Silicon-Based Micromachining Process for Flexible Electronics

Yang¹,

Wu²

2019

Micromachining

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The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Frasca

Leghziel

Arabadzhiev

et al. 2021

Sci Rep

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We present here, for the first time, a fabrication technique that allows manufacturing scallop free,non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. TSVs are among major technology players in modern high-volume manufacturing as they enable 3D chip integration. However, the usual standardized TSV fabrication process has to deal with scalloping, an imperfection in the sidewalls caused by the deep reactive ion etching. The presence of scalloping causes stress and field concentration in the dielectric barrier, thereby dramatically impacting the following TSV filling step, which is performed by means of electrochemical plating. So, we propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called “Michelangelo”, we obtained an extremely well polishing of the TSV holes, by reaching atomic-level smoothness and a record aspect ratio of 28:1. The Michelangelo step will thus drastically reduce the footprint of 3D structures and will allow unprecedented efficiency in 3D chip integration.

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