Cooperating Reduction Machines

Kluge, Werner E.

doi:10.1109/tc.1983.1676151

Cited by 17 publications

(3 citation statements)

References 11 publications

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“…The idea to use annotations (Burton (1987), Glauert et al (1987), Goguen et al (1986), Hudek & Smith (1986) or special functions (Kluge (1983), Vree & Hartel (1988)) which control the reduction order is certainly not new. Some of them are introduced on the level of the programming language (Burton (1987), Hudak & Smith (1986), Vree & Hartel (1988)) while others are introduced on the level of the computational model (Gianert et al (1987), Goguen et al (1986), Kluge (1983)). They all express that an indicated expression has to be shipped to another (or to some concrete) processor.…”

Section: Related Workmentioning

confidence: 99%

“…They all express that an indicated expression has to be shipped to another (or to some concrete) processor. Most annotations (Hudak & Smith (1986), Goguen et al (1986, Kluge (1983), Vree & Hartel (1988)) are only capable of generating strict hierarchical "divide-and-conquer parallelism". Non-hierarchical process structures are possa'ble in Burtan's proposal.…”

Section: Related Workmentioning

confidence: 99%

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Parallel graph rewriting on loosely coupled machine architectures

Eekelen

Plasmeijer

Smetsers

1991

Conditional and Typed Rewriting Systems

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Graph rewriting models are very suited to serve as the basic computational model for functional languages and their implementation. Graphs are used to share computations which is needed to make efficient implementations of functional languages on sequential hardware possible. When graphs are rewritten (reduced) on parallel loosely coupled machine architectures, subgraphs have to be copied from one processor to another such that sharing is lost. In this paper we introduce the notion of lazy copying. With lazy copying it is possible to duplicate a graph without duplicating work. Lazy copying can be combined with simple mmotations which control the order of reduction. In principle, only interleaved execution of the individual reduction steps is possible. However, a condition is deduced under which parallel execution is allowed. When only certain combinations of lazy copying and annotations are used it is guarantied that this so-called non-interference condition is fulfilled. Abbreviations for these combinations are introduced. Now complex process behavlours, such as process communication on a loosely coupled parallel machine architecture, can be modelled. This also includes a special case: modelling mnltlprocessing on a single processor. Arbitrary process topologies can be created. Synchronous and asyncbronons process communication can be modelled. The implementation of the language Concurrent Clean, which is based on the proposed graph rewriting model, has shown that complicated parallel algorithms which can go far beyond divide-and-conquar like applications can be expressed. 1 I n t r o d u c t i o n Ideally, a computational model of a language is a formal model as close as possible to both its semantics and its implementation, still it models only the essential aspects of them. In the following paragraphs it is explained why Graph Rewriting Systems (GRS*s) are suited to serve as a computational model of functional languages and their implementations. After that, GRS's are extended in order to deal with parallel evaluation. Graph rewriting systems and functional languages Our prime interests are functional languages and their implementation on sequential and parallel hardware. Traditionally. the pure lambda calculus (Church (1932/3). Barendregt (1984)) is considered to be a suitable model for these languages. However, in our opinion, some important aspects of functional languages and the way they are usually implemented, cannot be modelled with this calculus. In particular, the calculus itself lacks pattern matching and the notion of sharing of computations. Patterns contain in'tportant information for strictness analyTers (Ntcker (1988)). Sharing of computations is essential to obtain efficient implementations on traditional hardware (Fasel & Keller (1986)). Graph Rewriting systems are based on pattern matching and sharing. We believe that compared to the X-calculus graph rewriting systems (Barendregt et al. (1987a,b)) are better suited to serve as computational model for functional languages. In the past we have...

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Parallel graph rewriting on loosely coupled machine architectures

Eekelen

Plasmeijer

Smetsers

1991

Conditional and Typed Rewriting Systems

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“…The speed-up for divide-and-conquer algo rithms is also valid for other architectures with local memory [35,30], Experiments on our experimental parallel reduction machine have been conducted in order to measure the architecture constant and to study its effect on divide-and-conquer algorithms [17]. …”

Section: Sandwich Reduction S Trategymentioning

confidence: 99%

The dutch parallel reduction machine project

Barendregt

Eekelen

Plasmeijer

et al. 1987

Future Generation Computer Systems

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Realization of computers using programmable logic units

Yamada

Nakamura

Shigei

et al. 1987

Systems & Computers in Japan

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A key to speeding up the processing is how to realize the programmable hardware using both a pipelined processing scheme and a multiprocessor processing scheme for such special hardware as the fast Fourier transform (FFT) unit and the digital filter. This paper proposes a structure for the programmable logic unit (PLU) based on such an idea, where the computing program is mapped on the hardware, and the processing is performed by write/read of the operand data. For the computer using the proposed PLU, three kinds of conceivable processing algorithms are presented. On the other hand, considering the number of pins, the regularity of the circuits, and the recent progress in three‐dimensional VLSI technology, it is highly conceivable that the proposed PLU is realized by VLSI. Thus, from the viewpoint of program execution in the computer using PLU, the program is constructed of the instructions computed by the PLU and the control instructions executed by the main CPU, and the processing mechanism is described using a program example. A discussion is made on the processing time, and it is shown that the computer using the PLU can utilize the parallelism of the computation by PLU to reduce the processing time, compared with the computer not using PLU. Thus, the effectiveness of the computer using PLU is demonstrated.

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Cooperating Reduction Machines

Cited by 17 publications

References 11 publications

Parallel graph rewriting on loosely coupled machine architectures

Parallel graph rewriting on loosely coupled machine architectures

The dutch parallel reduction machine project

Realization of computers using programmable logic units

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