Realization of computers using programmable logic units

Abstract

A key to speeding up the processing is how to realize the programmable hardware using both a pipelined processing scheme and a multiprocessor processing scheme for such special hardware as the fast Fourier transform (FFT) unit and the digital filter. This paper proposes a structure for the programmable logic unit (PLU) based on such an idea, where the computing program is mapped on the hardware, and the processing is performed by write/read of the operand data. For the computer using the proposed PLU, three kinds of conceivable processing algorithms are presented. On the other hand, considering the number of pins, the regularity of the circuits, and the recent progress in three‐dimensional VLSI technology, it is highly conceivable that the proposed PLU is realized by VLSI. Thus, from the viewpoint of program execution in the computer using PLU, the program is constructed of the instructions computed by the PLU and the control instructions executed by the main CPU, and the processing mechanism is described using a program example. A discussion is made on the processing time, and it is shown that the computer using the PLU can utilize the parallelism of the computation by PLU to reduce the processing time, compared with the computer not using PLU. Thus, the effectiveness of the computer using PLU is demonstrated.