Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power

Dingler, A; Siddiq, Mohammad Abu Jafar; Niemier, Michael; Hu, Xiaobo Sharon; Alam, M.T.; Bernstein, Gary H.; Porod, Wolfgang

doi:10.1109/dft.2009.44

Cited by 10 publications

(5 citation statements)

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“…To summarize, distributing clock lines on multiple layers could eliminate irregularities in field distributions at the clock wire boundaries, and decrease the magnetic fields required to move a signal in an NML ensemble from one group to another. (As reported in [64], there can be a field minimum if two parallel lines are excited; with a multilayer approach, while there will always be some variation in field, this undesirable field drop could be significantly reduced. )…”

Section: Line Clocking: Clock Wire Layoutsmentioning

confidence: 86%

“…For example, distributing clock lines on multiple layers (figure 21(c)) could reduce field irregularities at clock wire boundaries and decrease the magnetic fields required to move a signal in an NML ensemble from one group to another. (As reported in [64], there can be a field minimum if two parallel lines are excited, and alternative wire layouts could eliminate said minimum. )…”

Section: Line Clocking: Conceptmentioning

confidence: 90%

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Nanomagnet logic: progress toward system-level integration

Niemier

Bernstein

Csaba

et al. 2011

J. Phys.: Condens. Matter

158

172

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Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

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Section: Line Clocking: Clock Wire Layoutsmentioning

confidence: 86%

Section: Line Clocking: Conceptmentioning

confidence: 90%

Nanomagnet logic: progress toward system-level integration

Niemier

Bernstein

Csaba

et al. 2011

J. Phys.: Condens. Matter

158

172

View full text Add to dashboard Cite

show abstract

“…However, for the latter we have shown in previous work [Dingler et al 2009b] that if we restrict each clock group to 8 magnets, successful propagation is possible. As discussed in Section 4.1, the output of a group of magnets in a wire ensemble can be a weaker driver than the input to that group; by reducing the number of magnets in each group, the output can drive all M devices.…”

Section: Magnet Spacingmentioning

confidence: 92%

“…As the yoke gets smaller, fewer magnets will lie over the yoke and be subjected to the field minima seen in Figure 4(d). Previous results suggested that if yoke width increases, e.g., from 50nm to 100nm, the external field strength required to control the exact same line of magnets could double [Dingler et al 2009b]. (Note that these results considered a dm/dt cutoff as discussed in the preceding.)…”

Section: Yoke Widthmentioning

confidence: 94%

“…Previous work in Dingler et al [2009b] scaled the spacing between magnets as the size of the magnets scaled-with 40 × 60 × 20nm 3 magnets the distance between devices was 8 nm, with 50 × 75 × 25nm 3 magnets the distance between devices was 10nm, and with 60 × 90 × 30nm 3 magnets the spacing between devices was 12nm. Here, we first discuss results from an expanded simulation space designed to address how different spacings could affect signal propagation and energy requirements given different sized magnets (a 30nm yoke is assumed for all simulations unless otherwise noted).…”

Section: Magnet Spacingmentioning

confidence: 99%

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Performance and Energy Impact of Locally Controlled NML Circuits

Dingler

Niemier

et al. 2011

J. Emerg. Technol. Comput. Syst.

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This article quantitatively considers the performance of nanomagnetic logic circuits within the context of realistic drive circuitry. We also demonstrate how one of the five fundamental tenets of digital logicpreventing unwanted feedback-can be satisfied by realistic drive circuitry. More specifically, different types of multiphase clocks are investigated and compared. Initial projections suggest that even with drive circuitry overhead, nanomagnet logic can outperform subthreshold CMOS in terms of energy delay productand paths to lower power exist.

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