Low power CMOS-magnetic nano-logic with increased bit controllability

Das, Jagannath; Alam, Syed Q.; Bhanja, Sanjukta

doi:10.1109/nano.2011.6144605

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Cited by 4 publications

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“…In this arrangement the easy and hard axis of every nanomagnet is aligned to the respective column and row in which the nano magnet is housed. Such arrangements are typically essential for applications like logic-in-memory [3]. We will address the constraint as the layout constraint and define it as follows:…”

Section: Introductionmentioning

confidence: 99%

Addressing the layout constraint problem when cascading logic gates in nanomagnetic logic

Das

Alam

Bhanja

2012

2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO)

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Nanomagnetic Logic (NML) uses ferromagnetic and anti ferromagnetic coupling to propagate information and to com pute logic. In this paper we have addressed a layout constraint problem that surfaces in NML due to magnetic coupling based logic computation. The layout constraint problem poses a severe challenge to designing high density low power cas caded logic. After defining the problem and explaining its cause and impact on NML designs, we have proposed a novel solution to the problem. This helps to design high density and low power cascaded NML circuits.

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Section: Introductionmentioning

confidence: 99%