Controller synthesis for an I/O-Based hierarchical system architecture

Perk, S.; Moor, Thomas; Schmidt, Ece Güran

doi:10.1109/wodes.2008.4605992

Cited by 12 publications

(11 citation statements)

References 10 publications

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“…• Functions to support the hierarchical synthesis methods of the authors [4], [5], [11], [12] are implemented as the libFAUDES plugins "hiosys" and "schmidt". Routines of general interest will be integrated in the library core in the near future.…”

Section: Further Development and Applicationsmentioning

confidence: 99%

libFAUDES — An open source C++ library for discrete event systems

Moor

Schmidt

Perk

2008

2008 9th International Workshop on Discrete Event Systems

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The libFAUDES (Friedrich-Alexander University Discrete Event Systems) library is an open source C++ software library for discrete event systems (DES) that is developed at the University of Erlangen-Nuremberg. The core library supports methods for the DES analysis and supervisor synthesis, while a built-in plugin mechanism allows of specialized library extensions. In this paper, we evaluate libFAUDES according to the benchmark examples provided for the Workshop on Discrete Event Systems 2008.

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Section: Further Development and Applicationsmentioning

confidence: 99%

libFAUDES — An open source C++ library for discrete event systems

Moor

Schmidt

Perk

2008

2008 9th International Workshop on Discrete Event Systems

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“…With the I/O based hierarchical structure from [22], each controller can be designed independently, and controllability and nonblocking is retained when the controllers are combined.…”

Section: Introductionmentioning

confidence: 99%

“…end if 22: end for 23: return T rue the algorithm moves to next state in P chk . If there was no F alse returned during the loop, the algorithm will consider it to be ALF and returns T rue.…”

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confidence: 99%

“…We will check the per state conditions (lines 10-12 and lines [17][18][19][20][21][22][23][24][25][26][27], and then if the states take us to two different states for a common σ transition (line 19), we check to see if the new states already have a tuple in V isited (line 19). If they do, either they are known to be equivalent or we have already processed the pair and added their requirements to P ending.…”

mentioning

confidence: 99%

“…If they do, either they are known to be equivalent or we have already processed the pair and added their requirements to P ending. If they do not, we add the pair to P ending and V isited (lines [20][21][22]. This ensures that a state pair is added to pending at most once, so we will terminate after a finite number of iterations as G cl has a finite statespace.…”

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confidence: 99%

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Sampled-Data Supervisory Control

Leduc

Wang

2010

IFAC Proceedings Volumes

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This thesis focuses on issues related to implementing theoretical Discrete-Event Systems (DES) supervisors, and the concurrency and timing delay issues involved.Sampled-data (SD) supervisory control deals with timed DES (TDES) systems where the supervisors will be implemented as SD controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs.In this thesis, we identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller.We then establish a formal representation of an SD controller as a Moore Finite State Machine (FSM), and describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller, as well as a set of modular controllers and show that they will produce equivalent output.Next, we capture the enablement and forcing action of a translated controller in the form of a TDES supervisory control map, and show that the closed-loop behavior of this map and the plant is the same as that of the plant and the original TDES supervisor. We also show that our method is robust with respect to nonblocking and certain variations in the actual behavior of our physical system.We also introduce a set of predicate-based algorithms to verify the SD controllability property, as well as certain other conditions that we require. We have created a software tool for verifying these conditions and provide the source code in the appendix. We have implemented these algorithms using binary decision diagrams (BDD).For illustrative purpose, we have produced a set of examples which fail the key conditions discussed in this thesis, as well as a successful application example based on a Flexible Manufacturing System. We also presented the corresponding FSM, iii iv translated from the example's supervisors.

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