Controller estimation for FPGA target architectures during high-level synthesis

Abstract

In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence, especially, if a certain data-path realization requires a huge number of states and/or control signals. This paper presents a new approach on controller estimation during high-level synthesis for FPGA-based target architectures. The estimator, presented in this paper can be invoked after or during every synthesis-step, i.e. allocation, scheduling and binding, respectively. By considering the controller influence on the overall area of a design, design space exploration can be made more accurate and less error prone. We present an approach for estimating area of the controller based on information which are easily accessible during each step of highlevel synthesis, so no explicit description of the controller, which usually will be generated after the binding, is necessary. This is particularly valuable in the allocation phase, where intensive design space explorations have to be done, based on fast and accurate estimates.

High-level synthesis for large bit-width multipliers on FPGAs

“…Now the problem becomes how to estimate the resource usage for the control logic. Menn et al [18] presented a method for estimating the resource usage based on the number of states in the design. Their method is more suitable in the control oriented design where there is strong correlation between the complexity of the control and number of states.…”