High-level synthesis for large bit-width multipliers on FPGAs

Abstract

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource costeffectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding

“…For a fair comparison, we also implemented the 256-bit point addition in the same Virtex-II technology. From Table 5 we can see that the speedup in our case with respect to the Beowulf implementation is 11.2 and the speedup with respect to the FPGA-embedded multiplier of [9] is 1.4. Note also that they would require a two-chip Virtex-II implementation, for point addition and point doubling, respectively, whereas our pipeline folding results in one FPGA chip design.…”

“…Virtex-4 delay of scalar point multiplication based on Virtex-II Pro FPGA. We compared our 256-bit point addition results to a multiprocessor implementation based on a 32-node Beowulf cluster [9]. The results shown in Table 5 also include their Virtex-II implementation which uses 144 18-bit embedded multipliers.…”

“…Cluster [9] Embedded Multiplier [9] Folded Pipeline in our case 196.72µs 24.56µs 17.512µs Other FPGA designs of the elliptic cryptosystem architectures are in [6,8]. Comparison with [6] is difficult because they use the embedded multipliers in a Spartan FPGA, whereas we use the older Virtex-II and do not use any embedded multipliers.…”

A Study of Large Width Unsigned Multipliers on FPGAs

“…References [7]- [13] have more detailed information about large width multipliers, further references are mentioned as we go.…”

Reconfigurable Architecture for Network processing

“…While increasing m, implementations become very time and resource consuming. Most of the known architectures concern the acceleration of the multiplication process by modifying the elliptic equations by changing the Z coordinate term [5], or by multiplication scalability [6], or by using many serial and parallel Arithmetic units [7], or using High parallel Karatsuba Multiplier [8], those based on the MassyOmura multipliers, or the work based on a hybrid multipliers approach, also some parallel approach approaches, or the new word level structure, or through the systolic architecture, or by using the half and add method, or by parallelizing both the add and double Montgomery algorithms [9].…”