Controlled oxide interlayer for improving reliability of SiO₂/GaN MOS devices

Abstract

Abstarct The impact of controlling Ga-oxide (GaO x ) interlayers in SiO2/GaO x /GaN gate stacks is investigated by means of physical and electrical characterizations. Direct deposition of SiO2 insulators produces thin GaO x interlayers, and subsequent oxidation treatment attains high-quality insulator/GaN interface. However, the Ga diffusion into the SiO2 layers severely degrades the breakdown characteristics of GaN-MOS devices. To improve reliability of such devices, we proposed a two-step procedure with the initial SiO2 deposition conducted under nitrogen-rich ambient, followed by thick SiO2 capping. We found that this two-step procedure enables nitrogen incorporation in the insulator/GaN interface to stabilize GaN surface. Consequently, the Ga diffusion into the SiO2 overlayer during the oxidation annealing is effectively suppressed. The proposed method allows us to achieve a SiO2/GaO x /GaN stacked structure of superior electrical property with improved Weibull distribution of an oxide breakdown field and with interface state density below 1010 cm−2 eV−1.

Effects of surface treatment on Fermi level pinning at metal/GaN interfaces formed on homoepitaxial GaN layers

“…However, even this kind of oxide layer can consist of multiple crystalline forms with disordered phases and Ga-related defects 28,30) . Therefore, an uncontrolled surface oxide layer may be a source of disorder at the GaN surface and metal/GaN interfaces, although a "well-controlled" native oxide layer has been reported to reduce the interface state density at the insulator/GaN interface [31][32][33] . According to the disorder-induced gap state (DIGS) model 8) , the origin of Fermi level pinning at the surface and interfaces is the gap states induced by disorder in chemical bonding.…”

Anomalous interface fixed charge generated by forming gas annealing in SiO2/GaN MOS devices

“…Figures 3(a For the present SiO 2 /GaN MOS structures, the initial frequency dispersion of the SiO 2 /GaN MOS device before FGA was small enough, and D it was below the detection limit (10 10 cm −2 • eV −1 ) of our measurement system, as previously reported. 31) It should be noted that although a slight shift was observed due to the electron injection into the oxide by applying a positive gate bias, the frequency dispersion was not appreciably changed by FGA, which suggests that D it had negligible impact on the negative V FB shift of the GaN MOS devices. These results imply that the positive charges at the SiO 2 /GaN interface generated by FGA are likely fixed oxide charges near the interface.…”

“…To suppress Ga diffusion into SiO 2 , which degrades its dielectric reliability, 30) we initially deposited nitrogen-incorporated SiO 2 (SiON) layers with a low O 2 flow ratio diluted by nitrogen gas (N 2 ). 31) SiON layers with a thickness of about 5 nm were deposited under the following conditions. The TEOS/O 2 flow rate was set to 0.5/10 sccm.…”

“…Post-deposition annealing (PDA) was carried out in O 2 ambient at 800 °C for 30 min, which resulted in the formation of stable GaO x interlayers. 31) Thereafter, the samples were subjected to PDA in FG (3% H 2 /N 2 ) at temperatures ranging from 200 °C to 800 °C for 30 min, and then Ni gate electrodes with a diameter of about 100 μm and Al back contacts were formed by vacuum evaporation. Here, some of the fabricated samples were not subjected to PDA in FG, but rather to post-metallization annealing (PMA) in FG or N 2 at 400 °C for 30 min after Ni electrode deposition.…”

X-ray photoelectron spectroscopy study on effects of ultra-high-pressure annealing on surface of Mg-ion-implanted GaN

“…Compared with other wide-band-gap semiconductors, e.g., SiC and diamond, which are also promising materials for power device applications, GaN has the advantage that it can be combined with other III-nitride alloys, such as AlGaN, InAlN, and InAlGaN, to provide an excellent heterointerface while generating a two-dimensional electron gas with a high electron mobility. Furthermore, an excellent MOS structure with an extremely minimized interface state density at the insulator/GaN interface can be obtained [4][5][6] . Even an excellent MOS gate high-electron-mobility transistor can also be achieved 7) .…”