Control of SSO noise through the use of on-chip decoupling cells

Abstract

The use of standard-cell CMOS on-chip decoupling YO cells produces a significant reduction in SSO Noise in a Networking ASIC design. The decoupling-to-active cell ratios are varied for analysis.

Mitigation of process variability effects using decoupling cells

“…Decoupling cells (Dcells) are widely adopted in several industrial designs as a powerful knob to reduce the noise on the power/ground supply rails and signal lines [10,11]. The use of decoupling cells also is explored on radiation-hardened designs to filter the single event transient (SET) pulses induced by low energy particles [12].…”

“…In this context, the main contribution of this work is to investigate the effectiveness of adopting decoupling cells to attenuate the process variability effects. To reach this goal, this work presents an evaluation of process variation impact at layout level in a set of gates considering two schematic settings: traditional and adding decoupling cells in the gate output [10][11][12]. Penalties regarding performance, power consumption, and area also are reported alongside process variability robustness.…”

A method and tool set for on-chip power noise and jitter estimation

“…Tbe noise due to the activity of the YO drivers and their "ve power/ground distribution system is simulated Using a variation of a Generic Package Model (GPM) method [2,3]. This allows for a -cation of the package model to closer repment the actual power structures in the finished package.…”