Control and data flow graph extraction for high-level synthesis

Namballa, R.K.; Ranganathan, N.; Ejnioui, A.

doi:10.1109/isvlsi.2004.1339528

Cited by 24 publications

(15 citation statements)

References 4 publications

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“…Translating a behavioral specification to the Register Transfer Level and deriving a data and control flow graph is shown in [23]. The behavioral description is written in a hardware description language, instead of a high-level programming language.…”

Section: Related Workmentioning

confidence: 99%

Performance Increase by Software Decomposition with Characteristics of Combinational Logic

Potthoff

Gremzow

Brandau

et al. 2015

2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC)

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Software development for multicore or multiprocessor systems is complex and error prone. The development of sequential source code is familiar and a proven procedure. The model presented in this paper can help to make use of current hardware architectures with existing software. This model makes a change in execution possible and could lead to hardware software co-design. This paper presents a way to decompose sequential software. The characteristics are used for new arrangements of the fragments and in software visualization. The visualization supports the developers in understanding internal dependencies. Some improvements in visual presentation by reducing complexity are discussed.

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Section: Related Workmentioning

confidence: 99%

Performance Increase by Software Decomposition with Characteristics of Combinational Logic

Potthoff

Gremzow

Brandau

et al. 2015

2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC)

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show abstract

“…Existing methods for the definition of the structures of control and data flow graphs are shown in [37][38][39][40][41][42][43]. The following techniques are suggested for obtaining the element level parameters.…”

Section: Obtaining Of Required Parametersmentioning

confidence: 99%

Probabilistic error propagation model for mechatronic systems

Morozov

Janschek

2014

Mechatronics

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“…Scheduling and allocation are operations on this CDFG representation. However, conventional CDFGs [28] do not provide a method for supporting parallel and timed constructs. This is because traditional HLS methods automatically extract parallelism from sequential specifications, and there is no ability to specify explicitly parallel and timed behaviors.…”

Section: Extending Cdfgs To Support Parallel Andmentioning

confidence: 99%

synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs

Sinha

Patel

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents a high-level synthesis framework called synASM that synthesizes abstract state machines (ASMs) to VHDL for field-programmable gate arrays (FPGAs). In particular, this paper focuses on the specification, scheduling, and synthesis of parallel and timed constructs. ASMs possess well-defined formal semantics for sequential and parallel computation, and their composition. We extend ASMs to support the specification of timing requirements, which we call timed constructs. We also describe the composition of timed constructs with sequential and parallel computation. A key contribution of this paper is the extension of the force-directed scheduling algorithm to support both parallel and timed constructs. We implement the synthesis back-end in synASM that targets FPGAs. Our experiments show improvements of up to 52% in lookup table usage and 34% in total area for certain examples.Index Terms-Force-directed scheduling, high-level synthesis, parallel and timed constructs.

show abstract

Control and data flow graph extraction for high-level synthesis

Cited by 24 publications

References 4 publications

Performance Increase by Software Decomposition with Characteristics of Combinational Logic

Performance Increase by Software Decomposition with Characteristics of Combinational Logic

Probabilistic error propagation model for mechatronic systems

synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs

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