synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs

Sinha, Raj; Patel, Hiren

doi:10.1109/tcad.2012.2198474

Cited by 8 publications

(5 citation statements)

References 24 publications

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“…Another category of HLS IRs uses finite state machines (FSMs) to model programs' execution schedules at the cycle level [9,32,37]. While such FSM representations are reminiscent of Calyx's control language, these IRs impose restrictions on the timing behavior of the operations inside the FSMs.…”

Section: Related Workmentioning

confidence: 99%

A Compiler Infrastructure for Accelerator Generators

Nigam,

Thomas,

et al. 2021

Preprint

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We present Calyx, a new intermediate language (IL) for compiling high-level programs into hardware designs. Calyx combines a hardware-like structural language with a software-like control flow representation with loops and conditionals. This split representation enables a new class of hardware-focused optimizations that require both structural and control flow information which are crucial for high-level programming models for hardware design. The Calyx compiler lowers control flow constructs using finite-state machines and generates synthesizable hardware descriptions.We have implemented Calyx in an optimizing compiler that translates high-level programs to hardware. We demonstrate Calyx using two DSL-to-RTL compilers, a systolic array generator and one for a recent imperative accelerator language, and compare them to equivalent designs generated using high-level synthesis (HLS). The systolic arrays are 4.6× faster and 1.11× larger on average than HLS implementations, and the HLS-like imperative language compiler is within a few factors of a highly optimized commercial HLS toolchain. We also describe three optimizations implemented in the Calyx compiler.

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Section: Related Workmentioning

confidence: 99%

A Compiler Infrastructure for Accelerator Generators

Nigam,

Thomas,

et al. 2021

Preprint

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“…In electronic system design the socalled High-Level Synthesis (HLS) [21][22][23]] is a typical implementation of this concept. An HLS algorithm is used to transform an algorithm level specification into a synthesizable RTL model.…”

Section: Algorithmic Modeling Of Asipsmentioning

confidence: 99%

A proposed synthesis method for Application-Specific Instruction Set Processors

Horváth

Hosszú

Kovács

2015

Microelectronics Journal

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a b s t r a c tDue to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

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“…In [21] was developed a framework for the synthesis of electronic systems at a high level based on abstract finite state machines. The framework called synASM is capable of generating a CDFG (Control Data Flow Graph) from hardware descriptions based on C language.…”

Section: Related Researchmentioning

confidence: 99%