CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties

Görgen, Ralph; Grüttner, Kim; Herrera, Fernando; Peñil, Pablo; Medina, Julio; Villar, Eugenio; Palermo, Gianluca; Fornaciari, William; Brandolese, Carlo; Gadioli, Davide; Bocchio, S.; Ceva, Luca; Azzoni, Paolo; Poncino, Massimo; Vinco, Sara; Macii, Enrico; Cusenza, Salvatore; Favaro, John; Valencia, R.; Sander, Ingo; Rosvall, Kathrin; Quaglia, Davide

doi:10.1109/dsd.2016.95

Cited by 5 publications

(7 citation statements)

References 18 publications

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“…Several works have been widely studying system's timing properties. Some researchers are mainly focused on generating timing properties such as Real Time (RT), latency, execution time, throughput, communication time, performance and etc., to reduce the verification process, state space and cost [40], [42], [53]. Other works instead use the timing properties to assess whether the system under verification is correctly functioning or not [41], [50], [52].…”

Section: Timing Aspectsmentioning

confidence: 99%

“…The methodology uses the selective abstraction concept to reduce complexity. [53] introduces a tool called CONTREX to complement current activities in the area of predictable computing platforms and segregation mechanisms with techniques to compute RT properties. CONTREX enables energy efficient and cost aware design through analysis and optimization of properties such as RT.…”

Section: Timing Aspectsmentioning

confidence: 99%

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Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

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Section: Timing Aspectsmentioning

confidence: 99%

Section: Timing Aspectsmentioning

confidence: 99%

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…1. Integration of mixed critical applications on single chip [18] separately from the underlying hardware resources. Therefore, it manages the hardware access and creates timing and spatial partitioning between the applications running on the same core.…”

Section: Safety Criticalmentioning

confidence: 99%

“…to certification standards and paves the way to the future industrialization of the technology. In the case of the CONTREX EU project [18], current activities in the area of predictable computing platforms and segregation mechanisms were complemented with techniques considering extra-functional properties such as real-time, power, and temperature for safety/certification in mixed-critical systems. In contrary to the SAFEPOWER proposal, while some safety measures were partly considered, no complete safety process was integrated to the overall design flow of the CONTREX project.…”

Section: Impact Of Low-power Capabilities On Dependabilitymentioning

confidence: 99%

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fakih

Lenz

Azkarate-Askasua

et al. 2017

Microprocessors and Microsystems

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With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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“…CON-TREX [3] or SafePower [4], analyze the execution of parallel applications with different criticality levels on such devices, having the goal of reducing their overall power consumption. Since these systems are often battery-driven and/or have constraints regarding size, weight and temperature, the configuration of their power management features plays a major role in system design, to save energy and to reduce system's temperature.…”

Section: Introductionmentioning

confidence: 99%

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

Schreiner

Fakih

Gruettner

et al. 2017

2017 Euromicro Conference on Digital System Design (DSD)

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Abstract-Today's Cyber-Physical Systems (CPS) are witnessing a growing complexity in terms of the number of components and computational power in order to meet the requirements of nowadays applications. For this reason and due to their energy efficiency, Multiprocessor system-on-chips (MPSoC) are becoming ubiquitous. Yet, since these systems are often used in batterydriven and/or small housing use cases, the correct configuration of their power management techniques is an important factor in system design and can be related to possible safety aspects of the system. This calls for an adequate test framework, which is able to observe the power management functionalities of CPS, even before the actual hardware platform is available. The use of virtual platforms for functional validation, that allows executing the CPS's real target platform compatible application binary code on a generic host computer, is currently being adopted by the industry. This work focuses on enhancing industrial OVP virtual platforms by a functional test framework of the power management techniques. We will demonstrate and evaluate how this framework maintains to observe the power management techniques of the system under test. The evaluation uses a Xilinx ZC702 board based on a Xilinx Zynq-7000 MPSoC and its correspondent virtual platform in OVP. Results show that the functional test framework is able to analyze the different modes of operation regarding the power management techniques of the Xilinx Zynq processing system.

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CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties

Cited by 5 publications

References 18 publications

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Towards Multidimensional Verification: Where Functional Meets Non-Functional

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

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