Contradiction analysis for constraint-based random simulation

Abstract

Constraint-based random simulation is state-of-the-art in verification of multi-million gate industrial designs. This method is based on stimulus generation by constraint solving. The resulting stimuli will particularly cover corner case test scenarios which are usually hard to identify manually by the verification engineer. Consequently, constraintbased random simulation will catch corner case bugs that would remain undetected otherwise. Therefore, the quality of design verification is increased significantly. However, in the process of constraint specification for a specific test scenario, the verification engineer is faced with the problem of over-constraining, i.e. the overall constraint specified for a test scenario has no solution. In this case the root cause of the contradiction has to be identified and resolved. Given the complexity of constraints used to describe test scenarios, this can be a very time-consuming process.In this paper we propose a fully automated contradiction analysis method. Our method determines all "non relevant" constraints and computes all reasons that lead to the over-constraining. Thus, we pinpoint the verification engineer to exactly the sets of constraints that have to be considered to resolve the over-constraining. Experiments have been conducted in a real-life SystemC-based verification environment at AMD Dresden Design Center. They demonstrate a significant reduction of the constraint contradiction debug time.

CRAVE: An advanced constrained random verification environment for SystemC

“…In [18] bit-vector operators have been added and the uniform distribution among all constraint solutions is ensured in all cases. An approach to determine the exact reasons in case of over-constraining has been presented in [19]. In [20] the BDD-based constraint-solver is replaced by a method which uses a generalization of Boolean Satisfiability (SAT).…”

Constraint-based platform variants specification for early system verification

“…In [18] entropy metrics to define coverage targets of internal signals is combined with a framework which uses small randomized XOR constraints to generate stimuli for inadequately stimulated circuit regions. The authors in [19] present a methodology to analyze contradictory constraints that occur in constraint-based random simulation. Actually all of the approaches in constraint-based random simulation are used to generate test and stimuli for fixed platforms.…”

The system verification methodology for advanced TLM verification

“…In [16] bit vector operators have been added and the uniform distribution among all constraint solutions is ensured in all cases. An approach to determine the exact reasons in case of overconstraining has been presented in [17]. In [37] the BDDbased constraint-solver is replaced by a method which uses a generalization of Boolean Satisfiability (SAT).…”